Model { Name "simident" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip on BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Thu Jul 16 18:19:20 1998" Creator "greg" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "rsingh" ModifiedDateFormat "%" LastModifiedDate "Thu Aug 21 09:07:26 2003" ModelVersionFormat "1.%" ConfigurationManager "none" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm.c" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "oneshot" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect off ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "VariableStepDiscrete" SolverMode "SingleTasking" StartTime "0.0" StopTime "200" MaxOrder 5 MaxStep "1e-2" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "1e-6" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[]" LoadInitialState off InitialState "[]" SaveTime off TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput off OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints off MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "none" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt off BooleanDataType off ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_unix.tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType DiscreteTransferFcn Numerator "[1]" Denominator "[1 0.5]" SampleTime "1" Realization "auto" RTWStateStorageClass "Auto" } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ShowAdditionalParam off ParameterDataTypeMode "Same as input" ParameterDataType "sfix(16)" ParameterScalingMode "Best Precision: Matrix-wise" ParameterScaling "2^0" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType Inport Port "1" PortDimensions "-1" SampleTime "-1" ShowAdditionalParam off LatchInput off DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Mux Inputs "4" DisplayOption "none" } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType RandomNumber Mean "0" Variance "1" Seed "0" SampleTime "-1" VectorParams1D on } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType SignalGenerator WaveForm "sine" Amplitude "1" Frequency "1" Units "Hertz" VectorParams1D on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "simident" Location [505, 82, 1143, 373] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name "AutoRegressive \nwith eXternal input\nmodel est" "imator" Ports [2] Position [510, 84, 565, 171] DropShadow on AncestorBlock "slident2/AutoRegressive \nwith eXternal input\n" "model estimator" SourceBlock "slident/AutoRegressive \nwith eXternal input\nm" "odel estimator" SourceType "ARX" order "[2 2 1]" HowOften "25" tso "0.05" npts "200" cbsim "Simulation" } Block { BlockType Reference Name "Band-Limited\nWhite Noise" Ports [0, 1] Position [65, 175, 95, 205] SourceBlock "simulink/Sources/Band-Limited\nWhite Noise" SourceType "Continuous White Noise." Cov "[0.001]" Ts "2*pi" seed "[23341]" VectorParams1D on } Block { BlockType Sum Name "Diff" Ports [2, 1] Position [155, 140, 175, 160] DropShadow on ShowName off } Block { BlockType DiscreteTransferFcn Name "Dis. Transfer Fcn" Position [220, 129, 420, 171] DropShadow on ShowName off Numerator "[1 2 3]" Denominator "[1 1.11 0.33 0.03]" SampleTime "0.05" } Block { BlockType SignalGenerator Name "Input signal" Position [50, 88, 95, 122] DropShadow on WaveForm "square" Amplitude "1.000000" Frequency "0.875000" Units "rad/sec" } Line { SrcBlock "Diff" SrcPort 1 DstBlock "Dis. Transfer Fcn" DstPort 1 } Line { SrcBlock "Dis. Transfer Fcn" SrcPort 1 DstBlock "AutoRegressive \nwith eXternal input\nmodel est" "imator" DstPort 2 } Line { SrcBlock "Input signal" SrcPort 1 Points [0, 0] Branch { Points [15, 0; 0, 40] DstBlock "Diff" DstPort 1 } Branch { DstBlock "AutoRegressive \nwith eXternal input\nmodel e" "stimator" DstPort 1 } } Line { SrcBlock "Band-Limited\nWhite Noise" SrcPort 1 Points [15, 0; 0, -35] DstBlock "Diff" DstPort 2 } Annotation { Name "Try different model\nestimators:" Position [540, 68] } Annotation { Name "Start the simulation to see an estimate of the " "filter:" Position [220, 28] } } }