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      Name		      "E_volts_in_bit_units"
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  Description		  "Analog-to-Digital Converter Quantization Algorithm"
"\n\nThe quantization algorithm in the model takes in a 0 to 5 volt signal and"
" outputs \na 12-bit digital word in a 16-bit signed integer. A value of 0 cor"
"responds to 0 Volts \nand a value of 4096 would correspond to 5 Volts. A chan"
"ge in the least \nsignificant bit (LSB) is about 1.2 mV. As 12 bits can only "
"reach the value of \n4095, the highest voltage that can be read by this devic"
"e is approximately \n4.9988 Volts. In order to have no more than 1/2 LSB erro"
"r, the quantizer changes \nvalues midway between each voltage point, resultin"
"g in a 1/2-width interval at \n0 Volts and a 3/2-width interval just below 5 "
"Volts.\n"
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  CloseFcn		  "if exist('adc_ploth')\n  if ishandle(adc_ploth)\n  "
"  close(adc_ploth)\n  end\n  clear adc_ploth\n  if exist('tout'), clear tout;"
" end\n  if exist('yout'), clear yout; end\nend\n"
  InitFcn		  "\n"
  StartFcn		  "if exist('adc_ploth')\n  if ishandle(adc_ploth)\n  "
"  close(adc_ploth)\n  end\n  clear adc_ploth\nend\n"
  StopFcn		  "if exist('yout')\n if isstruct(yout)\n  adc_ploth ="
" figure;\n  plot(yout.signals(1).values,double(yout.signals(2).values),'bo-')"
", grid, hold on, plot([0,4096],[0,4096],'g'), hold off\n  title(sprintf('Idea"
"lized A/D converter quantization algorithm \\n (Zoom in close with the mouse "
"to see behavior details)'))\n  zoom on\n end\nend\n"
  Created		  "Fri Mar 12 10:05:04 2004"
  Creator		  "The MathWorks Inc."
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "batserve"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Sat Jan 22 19:08:50 2005"
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	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 60; 275, 0]
	    DstBlock		    "Sum"
	    DstPort		    2
	  }
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Idealized ADC quantizer"
      Ports		      [1, 1]
      Position		      [245, 105, 305, 155]
      AttributesFormatString  "(settings: %<NumberOfConverterBits>-bit convert"
"er\\nVmin: %<Vmin>, Vmax: %<Vmax>)"
      SourceBlock	      "simulink_extras/Additional\nDiscrete/Idealized "
"ADC quantizer"
      SourceType	      "IdealADC"
      ShowPortLabels	      on
      NumberOfConverterBits   "12"
      Vmin		      "0"
      Vmax		      "5"
      OutputDataType	      "int16"
      OutputNegativeValues    off
    }
    Block {
      BlockType		      SubSystem
      Name		      "More Info"
      Ports		      []
      Position		      [15, 15, 39, 38]
      DropShadow	      on
      ShowName		      off
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "disp('?')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"More Info"
	Location		[74, 70, 720, 494]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Reference
	  Name			  "Model Info"
	  Ports			  []
	  Position		  [15, 19, 610, 408]
	  ShowName		  off
	  FontName		  "Arial"
	  SourceBlock		  "simulink/Model-Wide\nUtilities/Model Info"
	  SourceType		  "CMBlock"
	  ShowPortLabels	  "on"
	  InitialBlockCM	  "None"
	  BlockCM		  "None"
	  Frame			  "on"
	  DisplayStringWithTags	  "Model Description:\n-------------------\n\n"
"%<Description>"
	  MaskDisplayString	  "Model Description:\\n-------------------\\n"
"\\nAnalog-to-Digital Converter Quantization Algorithm\\n\\nThe quantization a"
"lgorithm in the model takes in a 0 to 5 volt signal and outputs \\na 12-bit d"
"igital word in a 16-bit signed integer. A value of 0 corresponds to 0 Volts "
"\\nand a value of 4096 would correspond to 5 Volts. A change in the least \\n"
"significant bit (LSB) is about 1.2 mV. As 12 bits can only reach the value of"
" \\n4095, the highest voltage that can be read by this device is approximatel"
"y \\n4.9988 Volts. In order to have no more than 1/2 LSB error, the quantizer"
" changes \\nvalues midway between each voltage point, resulting in a 1/2-widt"
"h interval at \\n0 Volts and a 3/2-width interval just below 5 Volts.\\n"
	  HorizontalTextAlignment "Left"
	  LeftAlignmentValue	  "0.02"
	  SourceBlockDiagram	  "sldemo_adc_quantize"
	  TagMaxNumber		  "20"
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Rescale volts to\nmatch ADC signal"
      Ports		      [1, 1]
      Position		      [245, 247, 305, 283]
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      System {
	Name			"Rescale volts to\nmatch ADC signal"
	Location		[722, 289, 1062, 387]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "V"
	  Position		  [65, 83, 95, 97]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Bias
	  Name			  "Bias"
	  Position		  [170, 75, 225, 105]
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Gain
	  Name			  "Re-Scale"
	  Position		  [290, 67, 355, 113]
	  Gain			  "4096/5"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Outport
	  Name			  "bit_units"
	  Position		  [500, 83, 530, 97]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Bias"
	  SrcPort		  1
	  DstBlock		  "Re-Scale"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "V"
	  SrcPort		  1
	  DstBlock		  "Bias"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Re-Scale"
	  SrcPort		  1
	  DstBlock		  "bit_units"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Sweep Across\nVoltage Range\n(Reference signal)"
      Ports		      [0, 1]
      Position		      [75, 115, 120, 145]
      SourceBlock	      "simulink/Sources/Repeating\nSequence"
      SourceType	      "Repeating table"
      ShowPortLabels	      on
      rep_seq_t		      "[0 7000]"
      rep_seq_y		      "[-0.25, 7]"
      Port {
	PortNumber		1
	Name			"V"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Outport
      Name		      "E_volts_in_bit_units"
      Position		      [575, 258, 605, 272]
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Block {
      BlockType		      Outport
      Name		      "E_bit_units"
      Position		      [575, 123, 605, 137]
      Port		      "2"
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Block {
      BlockType		      Outport
      Name		      "bit_edges"
      Position		      [575, 313, 605, 327]
      Port		      "3"
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Line {
      Name		      "V"
      Labels		      [0, 0]
      SrcBlock		      "Sweep Across\nVoltage Range\n(Reference signal)"
      SrcPort		      1
      Points		      [60, 0]
      Branch {
	Points			[0, 135]
	DstBlock		"Rescale volts to\nmatch ADC signal"
	DstPort			1
      }
      Branch {
	DstBlock		"Idealized ADC quantizer"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Idealized ADC quantizer"
      SrcPort		      1
      DstBlock		      "E_bit_units"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Rescale volts to\nmatch ADC signal"
      SrcPort		      1
      Points		      [0, 0; 60, 0]
      Branch {
	DstBlock		"E_volts_in_bit_units"
	DstPort			1
      }
      Branch {
	Points			[0, 55]
	DstBlock		"Find edges of \nbit transitions in time"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Find edges of \nbit transitions in time"
      SrcPort		      1
      DstBlock		      "bit_edges"
      DstPort		      1
    }
    Annotation {
      Name		      "Analog to Digital Converter (ADC)\nquanization "
"algorithm\n(zero conversion time)"
      Position		      [279, 54]
      FontName		      "Arial"
      FontSize		      16
      FontWeight	      "bold"
    }
    Annotation {
      Name		      "The blocks driving outports 1 and 3 convert the"
" \ncontinuous reference signal into equivalent \"bit units\" \nto capture bit"
" transitions in time so the plot \nshows the transitions clearly.\n\n\n"
      Position		      [389, 439]
      ForegroundColor	      "blue"
      FontName		      "Arial"
      FontSize		      16
      FontWeight	      "bold"
    }
    Annotation {
      Name		      "Run the simulation.\nVisualize quantization eff"
"ects \nwith the plot created after the run."
      Position		      [479, 194]
      ForegroundColor	      "blue"
      FontName		      "Arial"
      FontSize		      16
      FontWeight	      "bold"
    }
  }
}

# Finite State Machines
#
#    Stateflow Version 6.2 (R14SP2) dated Jan 21 2005, 03:46:19
#
#

Stateflow {

	machine {
		id                   		1
		name                 		"sldemo_adc_quantize"
		created              		"13-Mar-2004 07:06:42"
		isLibrary            		0
		firstTarget          		2
		sfVersion            		62014000
		sfDemoChecksum       		[3672735947 3125208993 1359995613 3788578574]
	}

	target {
		id                        		2
		name                      		"sfun"
		description               		"Default Simulink S-Function Target."
		machine                   		1
		linkNode                  		[1 0 3]
	}

	target {
		id                        		3
		name                      		"rtw"
		codeFlags                 		" comments=1 statebitsets=1 databitsets=1 emitlogicalops=1 el"
						"seifdetection=1 constantfolding=1 redundantloadelimination=0"
						" preserveconstantnames=0 preservenames=0 preservenameswithpa"
						"rent=0 exportcharts=0"
		machine                   		1
		linkNode                  		[1 2 0]
	}
}