;ELC ;;; Compiled by pot@pot.cnuce.cnr.it on Tue Mar 18 15:51:40 2003 ;;; from file /home/pot/gnu/emacs-pretest.new/lisp/progmodes/vhdl-mode.el ;;; in Emacs version 21.3 ;;; with bytecomp version 2.85.4.1 ;;; with all optimizations. ;;; This file uses dynamic docstrings, first added in Emacs 19.29. (if (and (boundp 'emacs-version) (< (aref emacs-version (1- (length emacs-version))) ?A) (or (and (boundp 'epoch::version) epoch::version) (string-lessp emacs-version "19.29"))) (error "`vhdl-mode.el' was compiled for Emacs 19.29 or later")) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; #@73 Set variables as in `custom-set-default' and call FUNCTIONS afterwards. (defalias 'vhdl-custom-set #[(variable value &rest functions) "\303\304!\203\304 \"\210\202\305 \"\210\n\205*\303\n@!\203\"\n@ \210\nA\211\204\306\207" [variable value functions fboundp custom-set-default set-default nil] 4 (#$ . 630)]) (byte-code "\300\301\302\303\304\305\306\307\310\311& \210\300\312\302\313\306\301%\207" [custom-declare-group vhdl nil "Customizations for VHDL Mode." :prefix "vhdl-" :group languages :version "20.4" vhdl-mode "Customizations for modes."] 10) #@252 *Non-nil enables electrification (automatic template generation). If nil, template generators can still be invoked through key bindings and menu. Is indicated in the modeline by `/e' after the mode name and can be toggled by `\[vhdl-electric-mode]'. (custom-declare-variable 'vhdl-electric-mode 't '(#$ . -1201) :type 'boolean :group 'vhdl-mode) #@133 *Non-nil enables stuttering. Is indicated in the modeline by `/s' after the mode name and can be toggled by `\[vhdl-stutter-mode]'. (custom-declare-variable 'vhdl-stutter-mode 't '(#$ . -1555) :type 'boolean :group 'vhdl-mode) #@90 *Non-nil means indentation can insert tabs. Overrides local variable `indent-tabs-mode'. (custom-declare-variable 'vhdl-indent-tabs-mode 'nil '(#$ . -1788) :type 'boolean :group 'vhdl-mode) (custom-declare-group 'vhdl-project nil "Customizations for projects." :group 'vhdl) #@813 *List of projects and their properties. Name : name of project Title : title of project (one-line string) Sources : a) source files : path + "/" + file name b) directory : path + "/" c) directory tree: "-r " + path + "/" Description: description of project (multi-line string) Project name and description are used to insert into the file header (see variable `vhdl-file-header'). Path and file name can contain wildcards `*' and `?'. Environment variables (e.g. "$EXAMPLE2") are resolved. The hierarchy browser shows the hierarchy of the design units found in `Sources'. If no directories or files are specified, the current directory is shown. NOTE: Reflect the new setting in the choice list of variable `vhdl-project' by restarting Emacs. (custom-declare-variable 'vhdl-project-alist ''(("example 1" "Project with individual source files" ("~/example1/vhdl/system.vhd" "~/example1/vhdl/component_*.vhd") "-------------------------------------------------------------------------------\n-- This is a multi-line project description\n-- that can be used as a project dependent part of the file header.\n") ("example 2" "Project where source files are located in two directories" ("$EXAMPLE2/vhdl/components/" "$EXAMPLE2/vhdl/system/") "") ("example 3" "Project where source files are located in some directory trees" ("-r ~/example3/*/vhdl/") "")) '(#$ . -2070) :type '(repeat (list :tag "Project" :indent 2 (string :tag "Name ") (string :tag "Title") (repeat :tag "Sources" :indent 4 (string :format "%v")) (string :tag "Description: (type `C-j' for newline)" :format "%t\n%v"))) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-update-mode-menu)) :group 'vhdl-project) #@352 *Specifies the default for the current project. Select a project name from the ones defined in variable `vhdl-project-alist'. Is used to determine the project title and description to be inserted in file headers and the source files/directories to be scanned in the hierarchy browser. The current project can also be changed temporarily in the menu. (custom-declare-variable 'vhdl-project '"" '(#$ . -3837) :type (let ((project-alist vhdl-project-alist) choice-list) (while project-alist (setq choice-list (cons (list 'const (car (car project-alist))) choice-list)) (setq project-alist (cdr project-alist))) (append '(choice (const :tag "None" "") (const :tag "--")) (nreverse choice-list))) :group 'vhdl-project) (custom-declare-group 'vhdl-compile nil "Customizations for compilation." :group 'vhdl) #@1389 *List of available VHDL compilers and their properties. Each list entry specifies the following items for a compiler: Compiler: Compiler Name : name used in variable `vhdl-compiler' to choose compiler Compile Command : command including options used for syntax analysis Make Command : command including options used instead of `make' (default) Generate Makefile: command to generate a Makefile (used by `make' command) From Directory : directory where compilation is run (must end with '/') Error Message: Regexp : regular expression to match error messages File Subexp Index: index of subexpression that matches the file name Line Subexp Index: index of subexpression that matches the line number File Message: Regexp : regular expression to match a file name message File Subexp Index: index of subexpression that matches the file name See also variable `vhdl-compiler-options' to add options to the compile command. Some compilers do not include the file name in the error message, but print out a file name message in advance. In this case, set "File Subexp Index" to 0 and fill out the "File Message" entries. A compiler is selected for syntax analysis (`\[vhdl-compile]') by assigning its name to variable `vhdl-compiler'. NOTE: Reflect the new setting in the choice list of variable `vhdl-compiler' by restarting Emacs. (custom-declare-variable 'vhdl-compiler-alist ''(("Cadence" "cv -file" "" "" "./" ("duluth: \\*E,[0-9]+ (\\(.+\\),\\([0-9]+\\)):" 1 2) ("" 0)) ("Ikos" "analyze" "" "" "./" ("E L\\([0-9]+\\)/C[0-9]+:" 0 1) ("^analyze +\\(.+ +\\)*\\(.+\\)$" 2)) ("ModelSim" "vcom" "" "vmake > Makefile" "./" ("\\(ERROR\\|WARNING\\)[^:]*: \\(.+\\)(\\([0-9]+\\)):" 2 3) ("" 0)) ("QuickHDL" "qvhcom" "" "qhmake >! Makefile" "./" ("\\(ERROR\\|WARNING\\)[^:]*: \\(.+\\)(\\([0-9]+\\)):" 2 3) ("" 0)) ("Synopsys" "vhdlan" "" "" "./" ("\\*\\*Error: vhdlan,[0-9]+ \\(.+\\)(\\([0-9]+\\)):" 1 2) ("" 0)) ("Vantage" "analyze -libfile vsslib.ini -src" "" "" "./" ("\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" 0 1) ("^ *Compiling \"\\(.+\\)\" " 1)) ("Viewlogic" "analyze -libfile vsslib.ini -src" "" "" "./" ("\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" 0 1) ("^ *Compiling \"\\(.+\\)\" " 1))) '(#$ . -4648) :type '(repeat (list :tag "Compiler" :indent 2 (string :tag "Compiler Name ") (string :tag "Compile Command ") (string :tag "Make Command ") (string :tag "Generate Makefile") (string :tag "From Directory " "./") (list :tag "Error Message" :indent 4 (regexp :tag "Regexp ") (integer :tag "File Subexp Index") (integer :tag "Line Subexp Index")) (list :tag "File Message" :indent 4 (regexp :tag "Regexp ") (integer :tag "File Subexp Index")))) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-update-mode-menu)) :group 'vhdl-compile) #@142 *Specifies the VHDL compiler to be used for syntax analysis. Select a compiler name from the ones defined in variable `vhdl-compiler-alist'. (custom-declare-variable 'vhdl-compiler '"ModelSim" '(#$ . -7495) :type (let ((compiler-alist vhdl-compiler-alist) choice-list) (while compiler-alist (setq choice-list (cons (list 'const (car (car compiler-alist))) choice-list)) (setq compiler-alist (cdr compiler-alist))) (append '(choice) (nreverse choice-list))) :group 'vhdl-compile) #@46 *Options to be added to the compile command. (custom-declare-variable 'vhdl-compiler-options '"" '(#$ . -7980) :type 'string :group 'vhdl-compile) (custom-declare-group 'vhdl-style nil "Customizations for code styles." :group 'vhdl) #@358 *VHDL standards used. Basic standard: VHDL'87 : IEEE Std 1076-1987 VHDL'93 : IEEE Std 1076-1993 Additional standards: VHDL-AMS : IEEE Std 1076.1 (analog-mixed-signal) Math Packages: IEEE Std 1076.2 (`math_real', `math_complex') NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations". (custom-declare-variable 'vhdl-standard ''(87 nil) '(#$ . -8220) :type '(list (choice :tag "Basic standard" (const :tag "VHDL'87" 87) (const :tag "VHDL'93" 93)) (set :tag "Additional standards" :indent 2 (const :tag "VHDL-AMS" ams) (const :tag "Math Packages" math))) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-template-map-init 'vhdl-mode-abbrev-table-init 'vhdl-template-construct-alist-init 'vhdl-template-package-alist-init 'vhdl-update-mode-menu 'vhdl-words-init 'vhdl-font-lock-init)) :group 'vhdl-style) #@110 *Amount of basic offset used for indentation. This value is used by + and - symbols in `vhdl-offsets-alist'. (custom-declare-variable 'vhdl-basic-offset '2 '(#$ . -9120) :type 'integer :group 'vhdl-style) #@114 *Non-nil means convert keywords to upper case. This is done when typed or expanded or by the fix case functions. (custom-declare-variable 'vhdl-upper-case-keywords 'nil '(#$ . -9332) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-abbrev-list-init)) :group 'vhdl-style) #@115 *Non-nil means convert standardized types to upper case. This is done when expanded or by the fix case functions. (custom-declare-variable 'vhdl-upper-case-types 'nil '(#$ . -9644) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-abbrev-list-init)) :group 'vhdl-style) #@120 *Non-nil means convert standardized attributes to upper case. This is done when expanded or by the fix case functions. (custom-declare-variable 'vhdl-upper-case-attributes 'nil '(#$ . -9954) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-abbrev-list-init)) :group 'vhdl-style) #@128 *Non-nil means convert standardized enumeration values to upper case. This is done when expanded or by the fix case functions. (custom-declare-variable 'vhdl-upper-case-enum-values 'nil '(#$ . -10274) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-abbrev-list-init)) :group 'vhdl-style) #@90 *Non-nil means convert standardized constants to upper case. This is done when expanded. (custom-declare-variable 'vhdl-upper-case-constants 't '(#$ . -10603) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-abbrev-list-init)) :group 'vhdl-style) (custom-declare-group 'vhdl-electric nil "Customizations for electrification." :group 'vhdl) #@170 *Type of keywords for which electrification is enabled. VHDL keywords: invoke built-in templates User keywords: invoke user models (see variable `vhdl-model-alist') (custom-declare-variable 'vhdl-electric-keywords ''(vhdl user) '(#$ . -10984) :type '(set (const :tag "VHDL keywords" vhdl) (const :tag "User keywords" user)) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-mode-abbrev-table-init)) :group 'vhdl-electric) #@267 *Constructs for which labels are to be queried. Template generators prompt for optional labels for: None : no constructs Processes only: processes only (also procedurals in VHDL-AMS) All constructs: all constructs with optional labels and keyword END (custom-declare-variable 'vhdl-optional-labels ''process '(#$ . -11435) :type '(choice (const :tag "None" none) (const :tag "Processes only" process) (const :tag "All constructs" all)) :group 'vhdl-electric) #@351 *Specifies whether to insert empty lines in some templates. This improves readability of code. Empty lines are inserted in: None : no constructs Design units only: entities, architectures, configurations, packages only All constructs : also all constructs with BEGIN...END parts Replaces variable `vhdl-additional-empty-lines'. (custom-declare-variable 'vhdl-insert-empty-lines ''unit '(#$ . -11916) :type '(choice (const :tag "None" none) (const :tag "Design units only" unit) (const :tag "All constructs" all)) :group 'vhdl-electric) #@285 *Non-nil means indent argument lists relative to opening parenthesis. That is, argument, association, and port lists start on the same line as the opening parenthesis and subsequent lines are indented accordingly. Otherwise, lists start on a new line and are indented as normal code. (custom-declare-variable 'vhdl-argument-list-indent 'nil '(#$ . -12481) :type 'boolean :group 'vhdl-electric) #@182 *Non-nil means write association lists with formal parameters. In templates, you are prompted for formal and actual parameters. If nil, only a list of actual parameters is entered. (custom-declare-variable 'vhdl-association-list-with-formals 't '(#$ . -12882) :type 'boolean :group 'vhdl-electric) #@64 *Non-nil means place parenthesis around condition expressions. (custom-declare-variable 'vhdl-conditions-in-parenthesis 'nil '(#$ . -13186) :type 'boolean :group 'vhdl-electric) #@34 *String to use for a logic zero. (custom-declare-variable 'vhdl-zero-string '"'0'" '(#$ . -13370) :type 'string :group 'vhdl-electric) #@33 *String to use for a logic one. (custom-declare-variable 'vhdl-one-string '"'1'" '(#$ . -13511) :type 'string :group 'vhdl-electric) (custom-declare-group 'vhdl-header nil "Customizations for file header." :group 'vhdl-electric) #@1235 *String or file to insert as file header. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted as file header. Type `C-j' for newlines. If the header contains RCS keywords, they may be written as Keyword if the header needs to be version controlled. The following keywords for template generation are supported: : replaced by the name of the buffer : replaced by the user name and email address (customize `mail-host-address' or `user-mail-address' if required) : replaced by user login name : replaced by contents of variable `vhdl-company-name' : replaced by the current date : replaced by title of current project (`vhdl-project') : replaced by description of current project (`vhdl-project') : replaced by contents of variable `vhdl-platform-spec' <... string> : replaced by a queried string (... is the prompt word) : final cursor position The (multi-line) project description can be used as a project dependent part of the file header and can also contain the above keywords. (custom-declare-variable 'vhdl-file-header '"-------------------------------------------------------------------------------\n-- Title : \n-- Project : <project>\n-------------------------------------------------------------------------------\n-- File : <filename>\n-- Author : <author>\n-- Company : <company>\n-- Last update: <date>\n-- Platform : <platform>\n<projectdesc>-------------------------------------------------------------------------------\n-- Description: <cursor>\n-------------------------------------------------------------------------------\n-- Revisions :\n-- Date Version Author Description\n-- <date> 1.0 <login> Created\n-------------------------------------------------------------------------------\n\n" '(#$ . -13748) :type 'string :group 'vhdl-header) #@239 *String or file to insert as file footer. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted as file footer (i.e. at the end of the file). Type `C-j' for newlines. (custom-declare-variable 'vhdl-file-footer '"" '(#$ . -15823) :type 'string :group 'vhdl-header) #@44 *Name of company to insert in file header. (custom-declare-variable 'vhdl-company-name '"" '(#$ . -16164) :type 'string :group 'vhdl-header) #@164 *Specification of VHDL platform to insert in file header. The platform specification should contain names and versions of the simulation and synthesis tools used. (custom-declare-variable 'vhdl-platform-spec '"" '(#$ . -16312) :type 'string :group 'vhdl-header) #@250 *Specifies the date format to use in the header. This string is passed as argument to the command `format-time-string'. For more information on format strings, see the documentation for the `format-time-string' command (C-h f `format-time-string'). (custom-declare-variable 'vhdl-date-format '"%Y/%m/%d" '(#$ . -16581) :type 'string :group 'vhdl-header) #@224 *Prefix string of modification date in VHDL file header. If actualization of the modification date is called (menu, `\[vhdl-template-modify]'), this string is searched and the rest of the line replaced by the current date. (custom-declare-variable 'vhdl-modify-date-prefix-string '"-- Last update: " '(#$ . -16942) :type 'string :group 'vhdl-header) #@220 *Non-nil means update the modification date when the buffer is saved. Calls function `\[vhdl-template-modify]'). NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-modify-date-on-saving 't '(#$ . -17299) :type 'boolean :group 'vhdl-header) (custom-declare-group 'vhdl-sequential-process nil "Customizations for sequential processes." :group 'vhdl-electric) #@64 *Specifies which kind of reset to use in sequential processes. (custom-declare-variable 'vhdl-reset-kind ''async '(#$ . -17748) :type '(choice (const :tag "None" none) (const :tag "Synchronous" sync) (const :tag "Asynchronous" async)) :group 'vhdl-sequential-process) #@84 *Non-nil means reset in sequential processes is active high. Nil means active low. (custom-declare-variable 'vhdl-reset-active-high 'nil '(#$ . -18022) :type 'boolean :group 'vhdl-sequential-process) #@92 *Non-nil means rising edge of clock triggers sequential processes. Nil means falling edge. (custom-declare-variable 'vhdl-clock-rising-edge 't '(#$ . -18228) :type 'boolean :group 'vhdl-sequential-process) #@107 *Syntax of the clock edge condition. Standard: "clk'event and clk = '1'" Function: "rising_edge(clk)" (custom-declare-variable 'vhdl-clock-edge-condition ''standard '(#$ . -18441) :type '(choice (const :tag "Standard" standard) (const :tag "Function" function)) :group 'vhdl-sequential-process) #@44 *Name of clock signal to use in templates. (custom-declare-variable 'vhdl-clock-name '"" '(#$ . -18746) :type 'string :group 'vhdl-sequential-process) #@44 *Name of reset signal to use in templates. (custom-declare-variable 'vhdl-reset-name '"" '(#$ . -18903) :type 'string :group 'vhdl-sequential-process) (custom-declare-group 'vhdl-model nil "Customizations for user models." :group 'vhdl) #@1271 *List of user models. VHDL models (templates) can be specified by the user in this list. They can be invoked from the menu, through key bindings (`C-c C-m ...'), or by keyword electrification (i.e. overriding existing or creating new keywords, see variable `vhdl-electric-keywords'). Name : name of model (string of words and spaces) String : string or name of file to be inserted as model (newline: `C-j') Key Binding: key binding to invoke model, added to prefix `C-c C-m' (must be in double-quotes, examples: "i", "\C-p", "\M-s") Keyword : keyword to invoke model The models can contain prompts to be queried. A prompt is of the form "<...>". A prompt that appears several times is queried once and replaced throughout the model. Special prompts are: <clock> : name specified in `vhdl-clock-name' (if not empty) <reset> : name specified in `vhdl-reset-name' (if not empty) <cursor>: final cursor position If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted. The code within the models should be correctly indented. Type `C-j' for newlines. NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-model-alist ''(("example model" "<label> : process (<clock>, <reset>)\nbegin -- process <label>\n if <reset> = '0' then -- asynchronous reset (active low)\n <cursor>\n elsif <clock>'event and <clock> = '1' then -- rising clock edge\n if <enable> = '1' then -- synchronous load\n\n end if;\n end if;\nend process <label>;" "e" "")) '(#$ . -19148) :type '(repeat (list :tag "Model" :indent 2 (string :tag "Name ") (string :tag "String : (type `C-j' for newline)" :format "%t\n%v") (sexp :tag "Key Binding" x) (string :tag "Keyword "))) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-model-map-init 'vhdl-model-defun 'vhdl-mode-abbrev-table-init 'vhdl-update-mode-menu)) :group 'vhdl-model) (custom-declare-group 'vhdl-port nil "Customizations for port transformation functions." :group 'vhdl) #@61 *Non-nil means include port comments when a port is pasted. (custom-declare-variable 'vhdl-include-port-comments 'nil '(#$ . -21296) :type 'boolean :group 'vhdl-port) #@72 *Non-nil means include signal direction in instantiations as comments. (custom-declare-variable 'vhdl-include-direction-comments 'nil '(#$ . -21469) :type 'boolean :group 'vhdl-port) (byte-code "\301B\302\301\207" [current-load-list vhdl-name-doc-string "\n\nFROM REGEXP is a regular expression matching the formal port name:\n `.*' matches the entire name\n `\\(...\\)' matches a substring\nTO STRING specifies the string to be inserted as actual port name:\n `\\&' means substitute original matched text\n `\\N' means substitute what matched the Nth `\\(...\\)'\nExamples:\n `.*' `\\&' leaves name as it is\n `.*' `\\&_i' attaches `_i' to original name\n `\\(.*\\)_[io]$' `\\1' strips off `_i' or `_o' from original name\n `.*' `' leaves name empty"] 2) (custom-declare-variable 'vhdl-actual-port-name ''(".*" . "\\&_i") (concat "*Specifies how actual port names are obtained from formal port names.\nIn a component instantiation, an actual port name can be obtained by\nmodifying the formal port name (e.g. attaching or stripping off a substring)." vhdl-name-doc-string) :type '(cons (regexp :tag "From Regexp") (string :tag "To String ")) :group 'vhdl-port) (custom-declare-variable 'vhdl-instance-name ''(".*" . "") (concat "*Specifies how an instance name is obtained.\nThe instance name can be obtained by modifying the name of the component to be\ninstantiated (e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the instance name is queried." vhdl-name-doc-string) :type '(cons (regexp :tag "From Regexp") (string :tag "To String ")) :group 'vhdl-port) (custom-declare-variable 'vhdl-testbench-entity-name ''(".*" . "\\&_tb") (concat "*Specifies how the test bench entity name is obtained.\nThe entity name of a test bench can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring)." vhdl-name-doc-string) :type '(cons (regexp :tag "From Regexp") (string :tag "To String ")) :group 'vhdl-port) (custom-declare-variable 'vhdl-testbench-architecture-name ''(".*" . "") (concat "*Specifies how the test bench architecture name is obtained.\nThe test bench architecture name can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the architecture name is queried." vhdl-name-doc-string) :type '(cons (regexp :tag "From Regexp") (string :tag "To String ")) :group 'vhdl-port) (custom-declare-variable 'vhdl-testbench-dut-name ''(".*" . "DUT") (concat "*Specifies how a DUT instance name is obtained.\nThe design-under-test instance name (i.e. the component instantiated in the\ntest bench) can be obtained by modifying the component name (e.g. attaching\nor stripping off a substring)." vhdl-name-doc-string) :type '(cons (regexp :tag "From Regexp") (string :tag "To String ")) :group 'vhdl-port) #@263 *String or file to be inserted as test bench entity header. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted at the beginning of the test bench entity template. Type `C-j' for newlines. (custom-declare-variable 'vhdl-testbench-entity-header '"" '(#$ . -24404) :type 'string :group 'vhdl-port) #@327 *String or file to be inserted as test bench architecture header. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted at the beginning of the test bench architecture template, if a separate file is created for the architecture. Type `C-j' for newlines. (custom-declare-variable 'vhdl-testbench-architecture-header '"" '(#$ . -24780) :type 'string :group 'vhdl-port) #@275 *String or file to be inserted in the test bench declarative part. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted in the test bench architecture before the BEGIN keyword. Type `C-j' for newlines. (custom-declare-variable 'vhdl-testbench-declarations '"" '(#$ . -25226) :type 'string :group 'vhdl-port) #@271 *String or file to be inserted in the test bench statement part. If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted in the test bench architecture before the END keyword. Type `C-j' for newlines. (custom-declare-variable 'vhdl-testbench-statements '"" '(#$ . -25613) :type 'string :group 'vhdl-port) #@73 *Non-nil means initialize signals with `0' when declared in test bench. (custom-declare-variable 'vhdl-testbench-initialize-signals 'nil '(#$ . -25993) :type 'boolean :group 'vhdl-port) #@299 *Specifies whether new files should be created for the test bench. Test bench entity and architecture are inserted: None : in current buffer Single file : in new single file Separate files: in two separate files Note that the files have the same name as the contained design unit. (custom-declare-variable 'vhdl-testbench-create-files ''single '(#$ . -26186) :type '(choice (const :tag "None" none) (const :tag "Single file" single) (const :tag "Separate files" separate)) :group 'vhdl-port) (custom-declare-group 'vhdl-comment nil "Customizations for comments." :group 'vhdl) #@70 *Non-nil means various templates automatically insert help comments. (custom-declare-variable 'vhdl-self-insert-comments 't '(#$ . -26786) :type 'boolean :group 'vhdl-comment) #@70 *Non-nil means various templates prompt for user definable comments. (custom-declare-variable 'vhdl-prompt-for-comments 't '(#$ . -26968) :type 'boolean :group 'vhdl-comment) #@188 *Column to indent inline comments to. Overrides local variable `comment-column'. NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-inline-comment-column '40 '(#$ . -27150) :type 'integer :group 'vhdl-comment) #@184 *End of comment column. Comments that exceed this column number are wrapped. NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-end-comment-column '79 '(#$ . -27453) :type 'integer :group 'vhdl-comment) (byte-code "\301B\302\303\304\305\306\307%\207" [current-load-list end-comment-column custom-declare-group vhdl-align nil "Customizations for alignment." :group vhdl] 6) #@69 *Non-nil means align some templates automatically after generation. (custom-declare-variable 'vhdl-auto-align 't '(#$ . -27920) :type 'boolean :group 'vhdl-align) #@129 *Non-nil means align groups of code lines separately. A group of code lines is a region of lines with no empty lines inbetween. (custom-declare-variable 'vhdl-align-groups 't '(#$ . -28090) :type 'boolean :group 'vhdl-align) (custom-declare-group 'vhdl-highlight nil "Customizations for highlighting." :group 'vhdl) #@549 *Non-nil means highlight VHDL keywords and other standardized words. The following faces are used: `font-lock-keyword-face' : keywords `font-lock-type-face' : standardized types `vhdl-font-lock-attribute-face' : standardized attributes `vhdl-font-lock-enumvalue-face' : standardized enumeration values `vhdl-font-lock-function-face' : standardized function and package names NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-keywords 't '(#$ . -28413) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@654 *Non-nil means highlight declaration names and construct labels. The following faces are used: `font-lock-function-name-face' : names in declarations of units, subprograms, components, as well as labels of VHDL constructs `font-lock-type-face' : names in type/nature declarations `vhdl-font-lock-attribute-face' : names in attribute declarations `font-lock-variable-name-face' : names in declarations of signals, variables, constants, subprogram parameters, generics, and ports NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-names 't '(#$ . -29160) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@363 *Non-nil means highlight words with special syntax. The words with syntax and color specified in variable `vhdl-special-syntax-alist' are highlighted accordingly. Can be used for visual support of naming conventions. NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-special-words 'nil '(#$ . -30009) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@427 *Non-nil means highlight forbidden words. The reserved words specified in variable `vhdl-forbidden-words' or having the syntax specified in variable `vhdl-forbidden-syntax' are highlighted in a warning color (face `vhdl-font-lock-reserved-words-face') to indicate not to use them. NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-forbidden-words 'nil '(#$ . -30577) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-words-init 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@332 *Non-nil means highlight Verilog keywords as reserved words. Verilog keywords are highlighted in a warning color (face `vhdl-font-lock-reserved-words-face') to indicate not to use them. NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-verilog-keywords 'nil '(#$ . -31228) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-words-init 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@461 *Non-nil means background-highlight code excluded from translation. That is, all code between "-- pragma translate_off" and "-- pragma translate_on" is highlighted using a different background color (face `vhdl-font-lock-translate-off-face'). Note: this might slow down on-the-fly fontification (and thus editing). NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-translate-off 'nil '(#$ . -31785) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@517 *Non-nil means consider case for highlighting. Possible trade-off: non-nil also upper-case VHDL words are highlighted, but case of words with special syntax is not considered nil only lower-case VHDL words are highlighted, but case of words with special syntax is considered Overrides local variable `font-lock-keywords-case-fold-search'. NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-highlight-case-sensitive 'nil '(#$ . -32451) :type 'boolean :group 'vhdl-highlight) #@1298 *List of special syntax to be highlighted. If variable `vhdl-highlight-special-words' is non-nil, words with the specified syntax (as regular expression) are highlighted in the corresponding color. Name : string of words and spaces Regexp : regular expression describing word syntax (e.g. "\w+_c" matches word with suffix "_c") Color (light): foreground color for light background (matching color examples: Gold3, Grey50, LimeGreen, Tomato, LightSeaGreen, DodgerBlue, Gold, PaleVioletRed) Color (dark) : foreground color for dark background (matching color examples: BurlyWood1, Grey80, Green, Coral, AquaMarine2, LightSkyBlue1, Yellow, PaleVioletRed1) Can be used for visual support of naming conventions, such as highlighting different kinds of signals (e.g. "Clk_c", "Rst_r") or objects (e.g. "Signal_s", "Variable_v", "Constant_c") by distinguishing them using name suffices. For each entry, a new face is generated with the specified colors and name "vhdl-font-lock-" + name + "-face". NOTE: Activate a changed regexp in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. All other changes require restarting Emacs. (custom-declare-variable 'vhdl-special-syntax-alist 'nil '(#$ . -33090) :type '(repeat (list :tag "Face" :indent 2 (string :tag "Name ") (regexp :tag "Regexp " "\\w+_") (string :tag "Color (light)") (string :tag "Color (dark) "))) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@332 *List of forbidden words to be highlighted. If variable `vhdl-highlight-forbidden-words' is non-nil, these reserved words are highlighted in a warning color to indicate not to use them. NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-forbidden-words ''nil '(#$ . -34748) :type '(repeat (string :format "%v")) :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-words-init 'vhdl-font-lock-init)) :group 'vhdl-highlight) #@464 *Syntax of forbidden words to be highlighted. If variable `vhdl-highlight-forbidden-words' is non-nil, words with this syntax are highlighted in a warning color to indicate not to use them. Can be used to highlight too long identifiers (e.g. "\w\w\w\w\w\w\w\w\w\w+" highlights identifiers with 10 or more characters). NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking. (custom-declare-variable 'vhdl-forbidden-syntax '"" '(#$ . -35318) :type 'regexp :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-words-init 'vhdl-font-lock-init)) :group 'vhdl-highlight) (custom-declare-group 'vhdl-menu nil "Customizations for speedbar and menues." :group 'vhdl) #@122 *Non-nil means open the speedbar automatically at startup. Alternatively, the speedbar can be opened from the VHDL menu. (custom-declare-variable 'vhdl-speedbar 'nil '(#$ . -36088) :type 'boolean :group 'vhdl-menu) #@125 *Non-nil means open the speedbar as hierarchy browser at startup. Otherwise, the speedbar is opened as normal file browser. (custom-declare-variable 'vhdl-speedbar-show-hierarchy 'nil '(#$ . -36310) :type 'boolean :group 'vhdl-menu) #@62 *Amount of indentation in hierarchy display of subcomponent. (custom-declare-variable 'vhdl-speedbar-hierarchy-indent '1 '(#$ . -36549) :type 'integer :group 'vhdl-menu) #@242 *Non-nil means add an index menu for a source file when loading. Alternatively, the speedbar can be used. Note that the index menu scans a file when it is opened, while speedbar only scans the file upon request. Does not work under XEmacs. (custom-declare-variable 'vhdl-index-menu 'nil '(#$ . -36726) :type 'boolean :group 'vhdl-menu) #@110 *Non-nil means add a menu of all source files in current directory. Alternatively, the speedbar can be used. (custom-declare-variable 'vhdl-source-file-menu 'nil '(#$ . -37070) :type 'boolean :group 'vhdl-menu) #@237 *Non-nil means add hideshow menu and functionality. Hideshow allows hiding code of VHDL design units. Does not work under XEmacs. NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-hideshow-menu 'nil '(#$ . -37288) :type 'boolean :group 'vhdl-menu) #@72 *Non-nil means hide all design units initially after a file is loaded. (custom-declare-variable 'vhdl-hide-all-init 'nil '(#$ . -37629) :type 'boolean :group 'vhdl-menu) (custom-declare-group 'vhdl-print nil "Customizations for printing." :group 'vhdl) #@162 *Non-nil means print code in two columns and landscape format. NOTE: Activate the new setting by restarting Emacs. Overrides `ps-print' settings locally. (custom-declare-variable 'vhdl-print-two-column 't '(#$ . -37889) :type 'boolean :group 'vhdl-print) #@169 *Non-nil means use an optimized set of faces for postscript printing. NOTE: Activate the new setting by restarting Emacs. Overrides `ps-print' settings locally. (custom-declare-variable 'vhdl-print-customize-faces 't '(#$ . -38158) :type 'boolean :group 'vhdl-print) (custom-declare-group 'vhdl-misc nil "Miscellaneous customizations." :group 'vhdl) #@522 *Non-nil means `TAB' does indentation, word completion and tab insertion. That is, if preceeding character is part of a word then complete word, else if not at beginning of line then insert tab, else if last command was a `TAB' or `RET' then dedent one step, else indent current line (i.e. `TAB' is bound to `vhdl-electric-tab'). If nil, TAB always indents current line (i.e. `TAB' is bound to `vhdl-indent-line'). NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-intelligent-tab 't '(#$ . -38522) :type 'boolean :group 'vhdl-misc) #@165 *Non-nil means word completion using `TAB' is case sensitive. That is, `TAB' completes words that start with the same letters and case. Otherwise, case is ignored. (custom-declare-variable 'vhdl-word-completion-case-sensitive 'nil '(#$ . -39149) :type 'boolean :group 'vhdl-misc) #@125 *Non-nil enables word completion in minibuffer (for template prompts). NOTE: Activate the new setting by restarting Emacs. (custom-declare-variable 'vhdl-word-completion-in-minibuffer 't '(#$ . -39436) :type 'boolean :group 'vhdl-misc) #@369 *Non-nil means consider the underscore character `_' as part of word. An identifier containing underscores is then treated as a single word in select and move operations. All parts of an identifier separated by underscore are treated as single words otherwise. NOTE: Activate the new setting in a VHDL buffer using the menu entry "Activate New Customizations" (custom-declare-variable 'vhdl-underscore-is-part-of-word 'nil '(#$ . -39680) :type 'boolean :set (lambda (variable value) (vhdl-custom-set variable value 'vhdl-mode-syntax-table-init)) :group 'vhdl-misc) (byte-code "\301\302\303\304\305\306%\210\307\302\310\311#\210\312\313\"\203�\307\302\314\311#\210\202$�\307\302\315\316#\210\312\313\"\2041�\307\302\317\311#\210\307\302\320\316#\210\307\302\321\311#\210\307\302\322\311#\207" [emacs-version custom-declare-group vhdl-related nil "Related general customizations." :group vhdl custom-add-to-group line-number-mode custom-variable string-match "XEmacs" paren-mode paren-showing custom-group transient-mark-mode ps-print mail-host-address user-mail-address] 6) #@27 VHDL Mode version number. (defconst vhdl-version "3.29" (#$ . 40770)) #@206 *Interval used to update progress status during long operations. If a number, percentage complete gets updated after each interval of that many seconds. To inhibit all messages, set this variable to nil. (defvar vhdl-progress-interval 1 (#$ . -40847)) #@56 *If non-nil, inhibits start up compatibility warnings. (defvar vhdl-inhibit-startup-warnings-p nil (#$ . -41106)) #@258 *If non-nil, all syntactic symbols must be found in `vhdl-offsets-alist'. If the syntactic symbol for a particular line does not match a symbol in the offsets alist, an error is generated, otherwise no error is reported and the syntactic symbol is ignored. (defvar vhdl-strict-syntax-p nil (#$ . -41227)) #@66 *If non-nil, syntactic info is echoed when the line is indented. (defvar vhdl-echo-syntactic-information-p nil (#$ . -41538)) #@143 Default settings for offsets of syntactic elements. Do not change this constant! See the variable `vhdl-offsets-alist' for more information. (defconst vhdl-offsets-alist-default '((string . -1000) (block-open . 0) (block-close . 0) (statement . 0) (statement-cont . vhdl-lineup-statement-cont) (statement-block-intro . +) (statement-case-intro . +) (case-alternative . +) (comment . vhdl-lineup-comment) (arglist-intro . +) (arglist-cont . 0) (arglist-cont-nonempty . vhdl-lineup-arglist) (arglist-close . vhdl-lineup-arglist) (entity . 0) (configuration . 0) (package . 0) (architecture . 0) (package-body . 0)) (#$ . 41671)) #@3157 *Association list of syntactic element symbols and indentation offsets. As described below, each cons cell in this list has the form: (SYNTACTIC-SYMBOL . OFFSET) When a line is indented, `vhdl-mode' first determines the syntactic context of the line by generating a list of symbols called syntactic elements. This list can contain more than one syntactic element and the global variable `vhdl-syntactic-context' contains the context list for the line being indented. Each element in this list is actually a cons cell of the syntactic symbol and a buffer position. This buffer position is call the relative indent point for the line. Some syntactic symbols may not have a relative indent point associated with them. After the syntactic context list for a line is generated, `vhdl-mode' calculates the absolute indentation for the line by looking at each syntactic element in the list. First, it compares the syntactic element against the SYNTACTIC-SYMBOL's in `vhdl-offsets-alist'. When it finds a match, it adds the OFFSET to the column of the relative indent point. The sum of this calculation for each element in the syntactic list is the absolute offset for line being indented. If the syntactic element does not match any in the `vhdl-offsets-alist', an error is generated if `vhdl-strict-syntax-p' is non-nil, otherwise the element is ignored. Actually, OFFSET can be an integer, a function, a variable, or one of the following symbols: `+', `-', `++', or `--'. These latter designate positive or negative multiples of `vhdl-basic-offset', respectively: *1, *-1, *2, and *-2. If OFFSET is a function, it is called with a single argument containing the cons of the syntactic element symbol and the relative indent point. The function should return an integer offset. Here is the current list of valid syntactic element symbols: string -- inside multi-line string block-open -- statement block open block-close -- statement block close statement -- a VHDL statement statement-cont -- a continuation of a VHDL statement statement-block-intro -- the first line in a new statement block statement-case-intro -- the first line in a case alternative block case-alternative -- a case statement alternative clause comment -- a line containing only a comment arglist-intro -- the first line in an argument list arglist-cont -- subsequent argument list lines when no arguments follow on the same line as the the arglist opening paren arglist-cont-nonempty -- subsequent argument list lines when at least one argument follows on the same line as the arglist opening paren arglist-close -- the solo close paren of an argument list entity -- inside an entity declaration configuration -- inside a configuration declaration package -- inside a package declaration architecture -- inside an architecture body package-body -- inside a package body (defvar vhdl-offsets-alist (copy-alist vhdl-offsets-alist-default) (#$ . -42307)) #@413 *Extra offset for line which contains only the start of a comment. Can contain an integer or a cons cell of the form: (NON-ANCHORED-OFFSET . ANCHORED-OFFSET) Where NON-ANCHORED-OFFSET is the amount of offset given to non-column-zero anchored comment-only lines, and ANCHORED-OFFSET is the amount of offset to give column-zero anchored comment-only lines. Just an integer as value is equivalent to (<val> . 0) (defvar vhdl-comment-only-line-offset 0 (#$ . -45552)) #@117 *Hook for user defined special indentation adjustments. This hook gets called after a line is indented by the mode. (defvar vhdl-special-indent-hook nil (#$ . -46026)) #@683 Styles of Indentation. Elements of this alist are of the form: (STYLE-STRING (VARIABLE . VALUE) [(VARIABLE . VALUE) ...]) where STYLE-STRING is a short descriptive string used to select a style, VARIABLE is any `vhdl-mode' variable, and VALUE is the intended value for that variable when using the selected style. There is one special case when VARIABLE is `vhdl-offsets-alist'. In this case, the VALUE is a list containing elements of the form: (SYNTACTIC-SYMBOL . VALUE) as described in `vhdl-offsets-alist'. These are passed directly to `vhdl-set-offset' so there is no need to set every syntactic symbol in your style, only those that are different from the default. (defvar vhdl-style-alist '(("IEEE" (vhdl-basic-offset . 4) (vhdl-offsets-alist))) (#$ . 46201)) (byte-code "\303\304\"\204�\305\304\306\307 \"B\211B*\303\207" [vhdl-style-alist varlist default assoc "Default" (vhdl-inhibit-startup-warnings-p vhdl-strict-syntax-p vhdl-echo-syntactic-information-p vhdl-basic-offset vhdl-offsets-alist vhdl-comment-only-line-offset) mapcar #[(var) "\211JB\207" [var] 2]] 5) #@30 *Hook called by `vhdl-mode'. (defvar vhdl-mode-hook nil (#$ . -47302)) #@44 Warnings to tell the user during start up. (defvar vhdl-startup-warnings nil (#$ . 47379)) #@57 Print out messages in variable `vhdl-startup-warnings'. (defalias 'vhdl-print-warnings #[nil "\211\203�\302\303 @P!\210 A\211\204�)G\304V\205�\302\305!\207" [vhdl-startup-warnings warnings message "WARNING: " 1 "WARNING: See warning messages in *Messages* buffer."] 4 (#$ . 47476)]) #@53 Add STRING to warning list `vhdl-startup-warnings'. (defalias 'vhdl-add-warning #[(string) " B\211\207" [string vhdl-startup-warnings] 2 (#$ . 47774)]) (byte-code ";\204 �\306\307\310!\210 <\204�\311\307\312!\210\n@G\313U\2039�\n\314\211\2035�\315\f@\316\" B\fA\211\204&� \237* @G\313U\203\\� \314\211\203X�\315\f@\317\" B\fA\211\204I� \237*\314\207" [vhdl-compiler vhdl-standard vhdl-model-alist new-alist old-alist vhdl-project-alist "ModelSim" vhdl-add-warning "Variable `vhdl-compiler' has changed format; customize again" (87 nil) "Variable `vhdl-standard' has changed format; customize again" 3 nil append ("") ("")] 4) #@50 Check if STANDARD is specified as used standard. (defalias 'vhdl-standard-p #[(standard) " @=\206� \211A@)>\207" [standard vhdl-standard x] 3 (#$ . 48422)]) (byte-code "\300\301\302\303#\210\304\305!\207" [put vhdl-standard-p byte-optimizer byte-compile-inline-expand require assoc] 4) #@108 Do whatever is necessary to keep the region active in XEmacs. Ignore byte-compiler warnings you might see. (defalias 'vhdl-keep-region-active #[nil "\301\300!\205 �\302\211\207" [zmacs-region-stays boundp t] 2 (#$ . 48719)]) (byte-code "\300\301!\204\n�\301\302M\210\300\207" [fboundp wildcard-to-regexp #[(wildcard) "\305\306\"\307 OG \203<� W\203<� H\n\f\310=\203&�\311\2023�\f\312=\2030�\313\2023�\314\f!P T)\202�\315\n\316Q+\207" [wildcard i result len ch string-match "[*?]" 0 42 "[^�]*" 63 "[^�]" char-to-string "\\`" "\\'"] 3 "Simplified version of `wildcard-to-regexp' from Emacs' `files.el'."]] 2) #@28 Keymap for VHDL templates. (defvar vhdl-template-map nil (#$ . 49345)) #@33 Initialize `vhdl-template-map'. (defalias 'vhdl-template-map-init #[nil "\304 \305\306\307#\210\305\310\311#\210\305\312\313#\210\305\314\315#\210\305\316\317#\210\305\320\321#\210\305\322\323#\210\305\324\325#\210\305\326\327#\210\305\330\331#\210\305\332\333#\210\305\334\335#\210\305\336\337#\210\305\340\341#\210\305\342\343#\210\305\344\345#\210\305\346\347#\210\305\350\351#\210\305\352\353#\210\305\354\355#\210\305\356\357#\210\305\360\361#\210\305\362\363#\210\305\364\365#\210\305\366\367#\210\305\370\371#\210\305\372\373#\210\305\374\375#\210\305\376\377#\210\305\201@�\201A�#\210\305\201B�\201C�#\210\305\201D�\201E�#\210\305\201F�\201G�#\210\305\201H�\201I�#\210\305\201J�\201K�#\210\305\201L�\201M�#\210\305\201N�\300#\210\305\201O�\201P�#\210\305\201Q�\201R�#\210\305\201S�\201T�#\210\305\201U�\201V�#\210\305\201W�\201X�#\210\305\201Y�\201Z�#\210\305\201[�\201\\�#\210\305\201]�\201^�#\210\305\201_�\201`�#\210\305\201a�\201b�#\210\305\201c�\201d�#\210\305\201e�\201f�#\210\305\201g�\201h�#\210\305\201i�\201j�#\210\305\201k�\201l�#\210\305\201m�\201n�#\210\305\201o�\201p�#\210\305\201q�\201r�#\210\305\201s�\201t�#\210\305\201u�\201v�#\210\305\201w�\201x�#\210\305\201y�\201z�#\210\305\201{�\201|�#\210\305\201}�\201~�#\210\305\201�\201\200�#\210\305\201\201�\201\202�#\210\305\201\203�\201\204�#\210\305\201\205�\201\206�#\210\305\201\207�\201\210�#\210\305\201\211�\201\212�#\210\305\201\213�\201\214�#\210\305\201\215�\201\216�#\210\305\201\217�\201\220�#\210\305\201\221�\201\222�#\210\305\201\223�\201\224�#\210\305\201\225�\201\226�#\210\201\227�\201\227�\n@=\206| \n\211A@)>)\203\356\305\201\230�\201\231�#\210\305\201\232�\201\233�#\210\305\201\234�\201\235�#\210\305\201\236�\201\237�#\210\305\201\240�\201\241�#\210\305\201\242�\201\243�#\210\305\201\244�\201\245�#\210\305\201\246�\201\247�#\210\305\201\250�\201\251�#\210\305\201\252�\201\253�#\210\305\201\254�\201\255�#\210\201\256�\201\256�\n@=\206 \n\211A@)>)\205\305\201\257�\201\260�#\210\305\201\261�\201\262�#\207" [vhdl-template-map standard vhdl-standard x make-sparse-keymap define-key "al" vhdl-template-alias "ar" vhdl-template-architecture "at" vhdl-template-assert "ad" vhdl-template-attribute-decl "as" vhdl-template-attribute-spec "bl" vhdl-template-block "ca" vhdl-template-case-is "cd" vhdl-template-component-decl "ci" vhdl-template-component-inst "cs" vhdl-template-conditional-signal-asst "Cb" vhdl-template-block-configuration "Cc" vhdl-template-component-conf "Cd" vhdl-template-configuration-decl "Cs" vhdl-template-configuration-spec "co" vhdl-template-constant "di" vhdl-template-disconnect "el" vhdl-template-else "ei" vhdl-template-elsif "en" vhdl-template-entity "ex" vhdl-template-exit "fi" vhdl-template-file "fg" vhdl-template-for-generate "fl" vhdl-template-for-loop "" vhdl-template-footer "fb" vhdl-template-function-body "fd" vhdl-template-function-decl "ge" vhdl-template-generic "gd" vhdl-template-group-decl "gt" vhdl-template-group-template "" vhdl-template-header "ig" vhdl-template-if-generate "it" vhdl-template-if-then "li" vhdl-template-library "lo" vhdl-template-bare-loop " " vhdl-template-modify "" vhdl-template-insert-date "ma" "ne" vhdl-template-next "ot" vhdl-template-others "Pd" vhdl-template-package-decl "Pb" vhdl-template-package-body "(" vhdl-template-paired-parens "po" vhdl-template-port "pb" vhdl-template-procedure-body "pd" vhdl-template-procedure-decl "pc" vhdl-template-process-comb "ps" vhdl-template-process-seq "rp" vhdl-template-report "rt" vhdl-template-return "ss" vhdl-template-selected-signal-asst "si" vhdl-template-signal "su" vhdl-template-subtype "ty" vhdl-template-type "us" vhdl-template-use "va" vhdl-template-variable "wa" vhdl-template-wait "wl" vhdl-template-while-loop "wi" vhdl-template-with "wc" vhdl-template-clocked-wait "b" vhdl-template-package-numeric-bit "n" vhdl-template-package-numeric-std "s" vhdl-template-package-std-logic-1164 "A" vhdl-template-package-std-logic-arith "M" vhdl-template-package-std-logic-misc "S" vhdl-template-package-std-logic-signed "T" vhdl-template-package-std-logic-textio "U" vhdl-template-package-std-logic-unsigned "t" vhdl-template-package-textio "n" vhdl-template-directive-translate-on "f" vhdl-template-directive-translate-off "N" vhdl-template-directive-synthesis-on "F" vhdl-template-directive-synthesis-off "" vhdl-template-search-prompt ams "br" vhdl-template-break "cu" vhdl-template-case-use "iu" vhdl-template-if-use "lm" vhdl-template-limit "na" vhdl-template-nature "pa" vhdl-template-procedural "qf" vhdl-template-quantity-free "qb" vhdl-template-quantity-branch "qs" vhdl-template-quantity-source "sn" vhdl-template-subnature "te" vhdl-template-terminal math "c" vhdl-template-package-math-complex "r" vhdl-template-package-math-real] 4 (#$ . 49422)]) (vhdl-template-map-init) #@177 Generate a Lisp function name. PREFIX, STRING and optional POSTFIX are concatenated by '-' and spaces in STRING are replaced by `-' and substrings are converted to lower case. (defalias 'vhdl-function-name #[(prefix string &optional postfix) "\304\305\n\"\203� \306\n\307\310\225O\227Q\n\311\224\312O\202� \203%� \306 Q\313 !)\207" [prefix name string postfix string-match "\\(\\w+\\)\\s-*\\(.*\\)" "-" 0 1 2 nil intern] 5 (#$ . 54345)]) #@25 Keymap for VHDL models. (defvar vhdl-model-map nil (#$ . 54796)) #@30 Initialize `vhdl-model-map'. (defalias 'vhdl-model-map-init #[nil "\304  \305\211\205\"� @\306\307\n8\310\311\n@\"#\210 A\211\204 �\305*\207" [vhdl-model-map vhdl-model-alist model model-alist make-sparse-keymap nil define-key 2 vhdl-function-name "vhdl-model"] 7 (#$ . 54867)]) (vhdl-model-map-init) #@23 Keymap for VHDL Mode. (defvar vhdl-mode-map nil (#$ . 55180)) #@29 Initialize `vhdl-mode-map'. (defalias 'vhdl-mode-map-init #[nil "\306 \307\310 #\210\307\311\n#\210\307\312\313#\210\307\314\315#\210\307\316\317#\210\307\320\321#\210\307\322\323#\210\307\324\325#\210\307\326\327#\210\307\330\331#\210\307\332\333#\210\307\334\335#\210\307\336\337#\210\340\341 \"\204^�\307\342\343#\210\307\344\345#\210\307\346\347#\210\307\350\351#\210\307\352\353#\210\307\354\355#\210\307\356\355#\210\307\357\360#\210\307\361\362#\210\307\363\364#\210\307\365\366#\210\307\367\370#\210\340\341 \"\203\260�\307\371\372#\210\202\266�\307\373\372#\210\307\374\375#\210\307\376\377#\210\307\201B�\201C�#\210\307\201D�\201E�#\210\307\201F�\201G�#\210\307\201H�\201I�#\210\307\201J�\201K�#\210\307\201L�\201M�#\210\307\201N�\201O�#\210\307\201P�\201Q�#\210\307\201R�\201S�#\210\307\201T�\201U�#\210\307\201V�\201W�#\210\307\201X�\201Y�#\210\307\201Z�\201[�#\210\307\201\\�\201]�#\210\307\201^�\201_�#\210\307\201`�\201a�#\210\307\201b�\201c�#\210\307\201d�\201e�#\210\307\201f�\201g�#\210\307\201h�\201i�#\210\307\201j�\201k�#\210\307\201l�\201m�#\210\307\201n�\201o�#\210\307\201p�\201q�#\210\307\201r�\201s�#\210\307\201t�\201u�#\210\307\201v�\201w�#\210\307\201x�\201y�#\210\307\201z�\201{�#\210\307\201|�\201}�#\210\307\201~�\201�#\210\307\201\200�\201\201�#\210\307\201\202�\201\203�#\210\f\203\307\201\204�\201\205�#\210\202'\307\201\204�\201I�#\210\307\201\206�\201\207�#\210\307\201\210�\201\211�#\210\307\201\212�\201\213�#\210\307\201\214�\201\215�#\210\307\201\216�\201\217�#\210\307\201\220�\201\221�#\210\307\201\222�\201\223�#\210\307\201\224�\201\225�#\210\201\226�\201\226�@@=\206\217 @\211AA@)>)\205\234\307\201\227�\201\230�#\207" [vhdl-mode-map vhdl-template-map vhdl-model-map emacs-version vhdl-intelligent-tab standard make-sparse-keymap define-key "" " " "\341" vhdl-beginning-of-statement "\345" vhdl-end-of-statement "\206" vhdl-forward-sexp "\202" vhdl-backward-sexp "\225" vhdl-backward-up-list "\201" vhdl-beginning-of-defun "\205" vhdl-end-of-defun "\210" vhdl-mark-defun "\221" vhdl-indent-sexp [backspace] backward-delete-char-untabify [delete] delete-char string-match "XEmacs" [M-delete] kill-word "" vhdl-electric-mode "" vhdl-stutter-mode " " vhdl-compile "\213" vhdl-make "" vhdl-port-copy "\367" "" vhdl-port-paste-entity "" vhdl-port-paste-component " " vhdl-port-paste-instance "" vhdl-port-paste-signals "\343" vhdl-port-paste-constants "\347" vhdl-port-paste-generic-map "" "" vhdl-port-paste-testbench "" vhdl-port-flatten vhdl-standard x "" vhdl-comment-uncomment-region "-" vhdl-comment-append-inline "\255" vhdl-comment-display-line "\211" vhdl-indent-line "\234" vhdl-indent-region "" vhdl-align-group "" vhdl-align-noindent-region "\201" vhdl-align-inline-comment-group "\201" vhdl-align-inline-comment-region "" vhdl-fixup-whitespace-region "\f" vhdl-line-kill "\f\367" vhdl-line-copy "\f" vhdl-line-yank "\f " vhdl-line-expand "\f" vhdl-line-transpose-next "\f" vhdl-line-transpose-previous "\f" vhdl-line-open "\f" goto-line "\f" vhdl-comment-uncomment-line "" vhdl-fix-case-region "" vhdl-fix-case-buffer "" vhdl-fontify-buffer "" vhdl-show-syntactic-information "" vhdl-doc-mode "" vhdl-version "" vhdl-beautify-region "" vhdl-beautify-buffer "\211" tab-to-tab-stop " " vhdl-template-insert-construct " " vhdl-template-insert-package " " vhdl-template-insert-directive " " vhdl-model-insert " " vhdl-electric-space " " vhdl-electric-tab " " vhdl-electric-return "-" vhdl-electric-dash "[" vhdl-electric-open-bracket "]" vhdl-electric-close-bracket "'" vhdl-electric-quote ";" vhdl-electric-semicolon "," vhdl-electric-comma "." vhdl-electric-period ams "=" vhdl-electric-equal] 4 (#$ . 55248)]) (vhdl-mode-map-init) #@42 Keymap for minibuffer used in VHDL Mode. (defvar vhdl-minibuffer-local-map (copy-keymap minibuffer-local-map) (#$ . 59117)) (byte-code "\203\n�\302 \303\304#\210\305\306\307\"\207" [vhdl-word-completion-in-minibuffer vhdl-minibuffer-local-map define-key " " vhdl-minibuffer-tab mapcar #[(sym) "\301\302\303#\210\301\304\303#\207" [sym put delete-selection t pending-delete] 4] (vhdl-electric-space vhdl-electric-tab vhdl-electric-return vhdl-electric-dash vhdl-electric-open-bracket vhdl-electric-close-bracket vhdl-electric-quote vhdl-electric-semicolon vhdl-electric-comma vhdl-electric-period vhdl-electric-equal)] 4) #@43 Syntax table used in `vhdl-mode' buffers. (defvar vhdl-mode-syntax-table nil (#$ . 59747)) #@38 Initialize `vhdl-mode-syntax-table'. (defalias 'vhdl-mode-syntax-table-init #[nil "\302 \303\304\305#\210\303\306\305#\210\303\307\305#\210\303\310\305#\210\303\311\305#\210\303\312\305#\210\303\313\305#\210\303\314\305#\210\303\315\305#\210\303\316\305#\210\303\317\305#\210\303\320\305#\210\303\321\305#\210\303\322\305#\210\303\323\305#\210\303\324\305#\210\303\325\326#\210 \203s�\303\327\330#\210\303\331\332#\210\303\333\334#\210\303\335\334#\210\303\336\337#\210\303\340\341#\210\303\342\343#\210\303\344\345#\210\303\346\347#\210\303\350\351#\207" [vhdl-mode-syntax-table vhdl-underscore-is-part-of-word make-syntax-table modify-syntax-entry 35 "." 36 37 38 39 42 43 46 47 58 59 60 61 62 92 124 34 "\"" 95 "w" 45 ". 12" 10 ">" 13 40 "()" 41 ")(" 91 "(]" 93 ")[" 123 "(}" 125 "){"] 4 (#$ . 59844)]) (vhdl-mode-syntax-table-init) #@65 Execute BODY with syntax table that includes `_' in word class. (defalias 'vhdl-ext-syntax-table '(macro . #[(&rest body) "\301\302\303\304\305\306BE\307BBBB\207" [body let (result) (modify-syntax-entry 95 "w" vhdl-mode-syntax-table) setq result progn ((when (not vhdl-underscore-is-part-of-word) (modify-syntax-entry 95 "_" vhdl-mode-syntax-table)) result)] 7 (#$ . 60714)])) #@59 Buffer local variable containing syntactic analysis list. (defvar vhdl-syntactic-context nil (#$ . 61098)) (make-variable-buffer-local 'vhdl-syntactic-context) #@45 Abbrev table to use in `vhdl-mode' buffers. (defvar vhdl-mode-abbrev-table nil (#$ . 61264)) #@38 Initialize `vhdl-mode-abbrev-table'. (defalias 'vhdl-mode-abbrev-table-init #[nil "\203�\306!\210\307\300\310\311 >\205�\312\311 >\205.�\313\313 @=\206)�\n \211A@)>)\205.�\314\315 >\205l� \316\211\211\203i�\317@8\211\320\232\204`�\320\321\322@@\323#\324FBA\211\204A�+#\"\207" [vhdl-mode-abbrev-table vhdl-electric-keywords standard vhdl-standard x vhdl-model-alist clear-abbrev-table define-abbrev-table append vhdl (("--" "" vhdl-template-display-comment-hook 0) ("abs" "" vhdl-template-default-hook 0) ("access" "" vhdl-template-default-hook 0) ("after" "" vhdl-template-default-hook 0) ("alias" "" vhdl-template-alias-hook 0) ("all" "" vhdl-template-default-hook 0) ("and" "" vhdl-template-default-hook 0) ("arch" "" vhdl-template-architecture-hook 0) ("architecture" "" vhdl-template-architecture-hook 0) ("array" "" vhdl-template-default-hook 0) ("assert" "" vhdl-template-assert-hook 0) ("attr" "" vhdl-template-attribute-hook 0) ("attribute" "" vhdl-template-attribute-hook 0) ("begin" "" vhdl-template-default-indent-hook 0) ("block" "" vhdl-template-block-hook 0) ("body" "" vhdl-template-default-hook 0) ("buffer" "" vhdl-template-default-hook 0) ("bus" "" vhdl-template-default-hook 0) ("case" "" vhdl-template-case-hook 0) ("comp" "" vhdl-template-component-hook 0) ("component" "" vhdl-template-component-hook 0) ("cond" "" vhdl-template-conditional-signal-asst-hook 0) ("conditional" "" vhdl-template-conditional-signal-asst-hook 0) ("conf" "" vhdl-template-configuration-hook 0) ("configuration" "" vhdl-template-configuration-hook 0) ("cons" "" vhdl-template-constant-hook 0) ("constant" "" vhdl-template-constant-hook 0) ("disconnect" "" vhdl-template-disconnect-hook 0) ("downto" "" vhdl-template-default-hook 0) ("else" "" vhdl-template-else-hook 0) ("elseif" "" vhdl-template-elsif-hook 0) ("elsif" "" vhdl-template-elsif-hook 0) ("end" "" vhdl-template-default-indent-hook 0) ("entity" "" vhdl-template-entity-hook 0) ("exit" "" vhdl-template-exit-hook 0) ("file" "" vhdl-template-file-hook 0) ("for" "" vhdl-template-for-hook 0) ("func" "" vhdl-template-function-hook 0) ("function" "" vhdl-template-function-hook 0) ("generic" "" vhdl-template-generic-hook 0) ("group" "" vhdl-template-group-hook 0) ("guarded" "" vhdl-template-default-hook 0) ("if" "" vhdl-template-if-hook 0) ("impure" "" vhdl-template-default-hook 0) ("in" "" vhdl-template-default-hook 0) ("inertial" "" vhdl-template-default-hook 0) ("inout" "" vhdl-template-default-hook 0) ("inst" "" vhdl-template-instance-hook 0) ("instance" "" vhdl-template-instance-hook 0) ("is" "" vhdl-template-default-hook 0) ("label" "" vhdl-template-default-hook 0) ("library" "" vhdl-template-library-hook 0) ("linkage" "" vhdl-template-default-hook 0) ("literal" "" vhdl-template-default-hook 0) ("loop" "" vhdl-template-bare-loop-hook 0) ("map" "" vhdl-template-map-hook 0) ("mod" "" vhdl-template-default-hook 0) ("nand" "" vhdl-template-default-hook 0) ("new" "" vhdl-template-default-hook 0) ("next" "" vhdl-template-next-hook 0) ("nor" "" vhdl-template-default-hook 0) ("not" "" vhdl-template-default-hook 0) ("null" "" vhdl-template-default-hook 0) ("of" "" vhdl-template-default-hook 0) ("on" "" vhdl-template-default-hook 0) ("open" "" vhdl-template-default-hook 0) ("or" "" vhdl-template-default-hook 0) ("others" "" vhdl-template-default-hook 0) ("out" "" vhdl-template-default-hook 0) ("pack" "" vhdl-template-package-hook 0) ("package" "" vhdl-template-package-hook 0) ("port" "" vhdl-template-port-hook 0) ("postponed" "" vhdl-template-default-hook 0) ("procedure" "" vhdl-template-procedure-hook 0) ("process" "" vhdl-template-process-hook 0) ("pure" "" vhdl-template-default-hook 0) ("range" "" vhdl-template-default-hook 0) ("record" "" vhdl-template-default-hook 0) ("register" "" vhdl-template-default-hook 0) ("reject" "" vhdl-template-default-hook 0) ("rem" "" vhdl-template-default-hook 0) ("report" "" vhdl-template-report-hook 0) ("return" "" vhdl-template-return-hook 0) ("rol" "" vhdl-template-default-hook 0) ("ror" "" vhdl-template-default-hook 0) ("select" "" vhdl-template-selected-signal-asst-hook 0) ("severity" "" vhdl-template-default-hook 0) ("shared" "" vhdl-template-default-hook 0) ("sig" "" vhdl-template-signal-hook 0) ("signal" "" vhdl-template-signal-hook 0) ("sla" "" vhdl-template-default-hook 0) ("sll" "" vhdl-template-default-hook 0) ("sra" "" vhdl-template-default-hook 0) ("srl" "" vhdl-template-default-hook 0) ("subtype" "" vhdl-template-subtype-hook 0) ("then" "" vhdl-template-default-hook 0) ("to" "" vhdl-template-default-hook 0) ("transport" "" vhdl-template-default-hook 0) ("type" "" vhdl-template-type-hook 0) ("unaffected" "" vhdl-template-default-hook 0) ("units" "" vhdl-template-default-hook 0) ("until" "" vhdl-template-default-hook 0) ("use" "" vhdl-template-use-hook 0) ("var" "" vhdl-template-variable-hook 0) ("variable" "" vhdl-template-variable-hook 0) ("wait" "" vhdl-template-wait-hook 0) ("when" "" vhdl-template-when-hook 0) ("while" "" vhdl-template-while-loop-hook 0) ("with" "" vhdl-template-with-hook 0) ("xnor" "" vhdl-template-default-hook 0) ("xor" "" vhdl-template-default-hook 0)) ams (("across" "" vhdl-template-default-hook 0) ("break" "" vhdl-template-break-hook 0) ("limit" "" vhdl-template-limit-hook 0) ("nature" "" vhdl-template-nature-hook 0) ("noise" "" vhdl-template-default-hook 0) ("procedural" "" vhdl-template-procedural-hook 0) ("quantity" "" vhdl-template-quantity-hook 0) ("reference" "" vhdl-template-default-hook 0) ("spectrum" "" vhdl-template-default-hook 0) ("subnature" "" vhdl-template-subnature-hook 0) ("terminal" "" vhdl-template-terminal-hook 0) ("through" "" vhdl-template-default-hook 0) ("tolerance" "" vhdl-template-default-hook 0)) user nil 3 "" vhdl-function-name "vhdl-model" "hook" 0 keyword abbrev-list alist] 12 (#$ . 61363)]) (vhdl-mode-abbrev-table-init) #@39 List of built-in construct templates. (defvar vhdl-template-construct-alist nil (#$ . 67251)) #@45 Initialize `vhdl-template-construct-alist'. (defalias 'vhdl-template-construct-alist-init #[nil "\304\305\306\306 @=\206� \211A@)>)\205�\307\"\211\207" [standard vhdl-standard x vhdl-template-construct-alist append (("alias declaration" vhdl-template-alias) ("architecture body" vhdl-template-architecture) ("assertion" vhdl-template-assert) ("attribute declaration" vhdl-template-attribute-decl) ("attribute specification" vhdl-template-attribute-spec) ("block configuration" vhdl-template-block-configuration) ("block statement" vhdl-template-block) ("case statement" vhdl-template-case-is) ("component configuration" vhdl-template-component-conf) ("component declaration" vhdl-template-component-decl) ("component instantiation statement" vhdl-template-component-inst) ("conditional signal assignment" vhdl-template-conditional-signal-asst) ("configuration declaration" vhdl-template-configuration-decl) ("configuration specification" vhdl-template-configuration-spec) ("constant declaration" vhdl-template-constant) ("disconnection specification" vhdl-template-disconnect) ("entity declaration" vhdl-template-entity) ("exit statement" vhdl-template-exit) ("file declaration" vhdl-template-file) ("generate statement" vhdl-template-generate) ("generic clause" vhdl-template-generic) ("group declaration" vhdl-template-group-decl) ("group template declaration" vhdl-template-group-template) ("if statement" vhdl-template-if-then) ("library clause" vhdl-template-library) ("loop statement" vhdl-template-loop) ("next statement" vhdl-template-next) ("package declaration" vhdl-template-package-decl) ("package body" vhdl-template-package-body) ("port clause" vhdl-template-port) ("process statement" vhdl-template-process) ("report statement" vhdl-template-report) ("return statement" vhdl-template-return) ("selected signal assignment" vhdl-template-selected-signal-asst) ("signal declaration" vhdl-template-signal) ("subprogram declaration" vhdl-template-subprogram-decl) ("subprogram body" vhdl-template-subprogram-body) ("subtype declaration" vhdl-template-subtype) ("type declaration" vhdl-template-type) ("use clause" vhdl-template-use) ("variable declaration" vhdl-template-variable) ("wait statement" vhdl-template-wait)) ams (("break statement" vhdl-template-break) ("nature declaration" vhdl-template-nature) ("quantity declaration" vhdl-template-quantity) ("simultaneous case statement" vhdl-template-case-use) ("simultaneous if statement" vhdl-template-if-use) ("simultaneous procedural statement" vhdl-template-procedural) ("step limit specification" vhdl-template-limit) ("subnature declaration" vhdl-template-subnature) ("terminal declaration" vhdl-template-terminal))] 5 (#$ . 67351)]) (vhdl-template-construct-alist-init) #@37 List of built-in package templates. (defvar vhdl-template-package-alist nil (#$ . 70102)) #@43 Initialize `vhdl-template-package-alist'. (defalias 'vhdl-template-package-alist-init #[nil "\304\305\306\306 @=\206� \211A@)>)\205�\307\"\211\207" [standard vhdl-standard x vhdl-template-package-alist append (("numeric_bit" vhdl-template-package-numeric-bit) ("numeric_std" vhdl-template-package-numeric-std) ("std_logic_1164" vhdl-template-package-std-logic-1164) ("std_logic_arith" vhdl-template-package-std-logic-arith) ("std_logic_misc" vhdl-template-package-std-logic-misc) ("std_logic_signed" vhdl-template-package-std-logic-signed) ("std_logic_textio" vhdl-template-package-std-logic-textio) ("std_logic_unsigned" vhdl-template-package-std-logic-unsigned) ("textio" vhdl-template-package-textio)) math (("math_complex" vhdl-template-package-math-complex) ("math_real" vhdl-template-package-math-real))] 5 (#$ . 70198)]) (vhdl-template-package-alist-init) #@39 List of built-in directive templates. (defvar vhdl-template-directive-alist (append '(("translate_on" vhdl-template-directive-translate-on) ("translate_off" vhdl-template-directive-translate-off) ("synthesis_on" vhdl-template-directive-synthesis-on) ("synthesis_off" vhdl-template-directive-synthesis-off))) (#$ . 71073)) #@54 Call the customize function with `vhdl' as argument. (defalias 'vhdl-customize #[nil "\300\301!\207" [customize-browse vhdl] 2 (#$ . 71401) nil]) #@69 Create a full customization menu for VHDL, insert it into the menu. (defalias 'vhdl-create-customize-menu #[nil "\300\301!\203�\302\303\304\305\301\306!\307BB#\207\310\311!\207" [fboundp customize-menu-create easy-menu-change ("VHDL") "Customize" ["Browse VHDL Group..." vhdl-customize t] vhdl ("--" ["Activate New Customizations" vhdl-activate-customizations t]) error "Cannot expand menu (outdated version of cus-edit.el)"] 6 (#$ . 71553) nil]) #@24 Create VHDL Mode menu. (defalias 'vhdl-create-mode-menu #[nil "\306\307\310\311\312\313\211\211\203+� @@\314 \315 D\316\317\320\321\322 E&\nB A\211\204�\323\310\nBB\211\237+\"\310\324\325\326\310\327\330\310\331\332\333\310\311\334\f\313\211\211\203j� @@\314 \335\336 E\316\317\320\321\336 E&\nB A\211\204M�\337\310\nBB\211\237+\"\257\f\310\311\340\341@\341A@=\206\217�@A\211BA@)>)\205\224�\342\343\311\344\345@\345A@=\206\255�@A\211BA@)>)\205\262�\346\347#C\350%\311\351C\313\211D\211E\203\353�E@D\314D@\352\353D@\"\354\355\356\357D8!P$\nBEA\211E\204\306�\311\n\237\360\"\211+\"\361\310\362\363\364\310\365\366\367\370\310\371\372\310\373\374\375\310\376\310\377\257\207" [vhdl-project-alist name menu-alist project-alist vhdl-compiler-alist comp-alist "VHDL" ("Mode" ["Electric" vhdl-electric-mode :style toggle :selected vhdl-electric-mode] ["Stutter" vhdl-stutter-mode :style toggle :selected vhdl-stutter-mode]) "--" append ("Project" ["None" (vhdl-project-switch "") :style radio :selected (equal vhdl-project "")] "--") nil vector vhdl-project-switch :style radio :selected equal vhdl-project ["Add Project..." (customize-variable 'vhdl-project-alist) t] "Compile" ["Compile Buffer" vhdl-compile t] ["Stop Compilation" kill-compilation t] ["Make" vhdl-make t] ["Generate Makefile" vhdl-generate-makefile t] ["Next Error" next-error t] ["Previous Error" previous-error t] ["First Error" first-error t] ("Compiler") setq vhdl-compiler ["Add Compiler..." (customize-variable 'vhdl-compiler-alist) t] ("Template" ("VHDL Construct 1" ["Alias" vhdl-template-alias t] ["Architecture" vhdl-template-architecture t] ["Assert" vhdl-template-assert t] ["Attribute (Decl)" vhdl-template-attribute-decl t] ["Attribute (Spec)" vhdl-template-attribute-spec t] ["Block" vhdl-template-block t] ["Case" vhdl-template-case-is t] ["Component (Decl)" vhdl-template-component-decl t] ["(Component) Instance" vhdl-template-component-inst t] ["Conditional (Signal Asst)" vhdl-template-conditional-signal-asst t] ["Configuration (Block)" vhdl-template-block-configuration t] ["Configuration (Comp)" vhdl-template-component-conf t] ["Configuration (Decl)" vhdl-template-configuration-decl t] ["Configuration (Spec)" vhdl-template-configuration-spec t] ["Constant" vhdl-template-constant t] ["Disconnect" vhdl-template-disconnect t] ["Else" vhdl-template-else t] ["Elsif" vhdl-template-elsif t] ["Entity" vhdl-template-entity t] ["Exit" vhdl-template-exit t] ["File" vhdl-template-file t] ["For (Generate)" vhdl-template-for-generate t] ["For (Loop)" vhdl-template-for-loop t] ["Function (Body)" vhdl-template-function-body t] ["Function (Decl)" vhdl-template-function-decl t] ["Generic" vhdl-template-generic t] ["Group (Decl)" vhdl-template-group-decl t] ["Group (Template)" vhdl-template-group-template t]) ("VHDL Construct 2" ["If (Generate)" vhdl-template-if-generate t] ["If (Then)" vhdl-template-if-then t] ["Library" vhdl-template-library t] ["Loop" vhdl-template-bare-loop t] ["Map" vhdl-template-map t] ["Next" vhdl-template-next t] ["(Others)" vhdl-template-others t] ["Package (Decl)" vhdl-template-package-decl t] ["Package (Body)" vhdl-template-package-body t] ["Port" vhdl-template-port t] ["Procedure (Body)" vhdl-template-procedure-body t] ["Procedure (Decl)" vhdl-template-procedure-decl t] ["Process (Comb)" vhdl-template-process-comb t] ["Process (Seq)" vhdl-template-process-seq t] ["Report" vhdl-template-report t] ["Return" vhdl-template-return t] ["Select" vhdl-template-selected-signal-asst t] ["Signal" vhdl-template-signal t] ["Subtype" vhdl-template-subtype t] ["Type" vhdl-template-type t] ["Use" vhdl-template-use t] ["Variable" vhdl-template-variable t] ["Wait" vhdl-template-wait t] ["(Clocked Wait)" vhdl-template-clocked-wait t] ["When" vhdl-template-when t] ["While (Loop)" vhdl-template-while-loop t] ["With" vhdl-template-with t])) ams (("VHDL-AMS Construct" ["Break" vhdl-template-break t] ["Case (Use)" vhdl-template-case-use t] ["If (Use)" vhdl-template-if-use t] ["Limit" vhdl-template-limit t] ["Nature" vhdl-template-nature t] ["Procedural" vhdl-template-procedural t] ["Quantity (Free)" vhdl-template-quantity-free t] ["Quantity (Branch)" vhdl-template-quantity-branch t] ["Quantity (Source)" vhdl-template-quantity-source t] ["Subnature" vhdl-template-subnature t] ["Terminal" vhdl-template-terminal t])) (["Insert Construct" vhdl-template-insert-construct :keys "C-c C-i C-c"] "--") ("Package") math (["math_complex" vhdl-template-package-math-complex t] ["math_real" vhdl-template-package-math-real t]) (["numeric_bit" vhdl-template-package-numeric-bit t] ["numeric_std" vhdl-template-package-numeric-std t] ["std_logic_1164" vhdl-template-package-std-logic-1164 t] ["textio" vhdl-template-package-textio t] "--" ["std_logic_arith" vhdl-template-package-std-logic-arith t] ["std_logic_signed" vhdl-template-package-std-logic-signed t] ["std_logic_unsigned" vhdl-template-package-std-logic-unsigned t] ["std_logic_misc" vhdl-template-package-std-logic-misc t] ["std_logic_textio" vhdl-template-package-std-logic-textio t] "--" ["Insert Package" vhdl-template-insert-package :keys "C-c C-i C-p"]) (("Directive" ["translate_on" vhdl-template-directive-translate-on t] ["translate_off" vhdl-template-directive-translate-off t] ["synthesis_on" vhdl-template-directive-synthesis-on t] ["synthesis_off" vhdl-template-directive-synthesis-off t] "--" ["Insert Directive" vhdl-template-insert-directive :keys "C-c C-i C-d"]) "--" ["Insert Header" vhdl-template-header :keys "C-c C-t C-h"] ["Insert Footer" vhdl-template-footer t] ["Insert Date" vhdl-template-insert-date t] ["Modify Date" vhdl-template-modify :keys "C-c C-t C-m"] "--" ["Query Next Prompt" vhdl-template-search-prompt t]) ("Model") vhdl-function-name "vhdl-model" :keys "C-c C-m " key-description 2 ("--" ["Insert Model" vhdl-model-insert :keys "C-c C-i C-m"] ["Add Model..." (customize-variable 'vhdl-model-alist) t]) ("Port" ["Copy" vhdl-port-copy t] "--" ["Paste As Entity" vhdl-port-paste-entity vhdl-port-list] ["Paste As Component" vhdl-port-paste-component vhdl-port-list] ["Paste As Instance" vhdl-port-paste-instance :keys "C-c C-p C-i" :active vhdl-port-list] ["Paste As Signals" vhdl-port-paste-signals vhdl-port-list] ["Paste As Constants" vhdl-port-paste-constants vhdl-port-list] ["Paste As Generic Map" vhdl-port-paste-generic-map vhdl-port-list] ["Paste As Test Bench" vhdl-port-paste-testbench vhdl-port-list] "--" ["Flatten" vhdl-port-flatten vhdl-port-list]) ("Comment" ["(Un)Comment Out Region" vhdl-comment-uncomment-region (mark)] "--" ["Insert Inline Comment" vhdl-comment-append-inline t] ["Insert Horizontal Line" vhdl-comment-display-line t] ["Insert Display Comment" vhdl-comment-display t] "--" ["Fill Comment" fill-paragraph t] ["Fill Comment Region" fill-region (mark)] ["Kill Comment Region" vhdl-comment-kill-region (mark)] ["Kill Inline Comment Region" vhdl-comment-kill-inline-region (mark)]) ("Line" ["Kill" vhdl-line-kill t] ["Copy" vhdl-line-copy t] ["Yank" vhdl-line-yank t] ["Expand" vhdl-line-expand t] "--" ["Transpose Next" vhdl-line-transpose-next t] ["Transpose Prev" vhdl-line-transpose-previous t] ["Open" vhdl-line-open t] ["Join" delete-indentation t] "--" ["Goto" goto-line t] ["(Un)Comment Out" vhdl-comment-uncomment-line t]) ("Move" ["Forward Statement" vhdl-end-of-statement t] ["Backward Statement" vhdl-beginning-of-statement t] ["Forward Expression" vhdl-forward-sexp t] ["Backward Expression" vhdl-backward-sexp t] ["Forward Function" vhdl-end-of-defun t] ["Backward Function" vhdl-beginning-of-defun t] ["Mark Function" vhdl-mark-defun t]) ("Indent" ["Line" vhdl-indent-line t] ["Region" vhdl-indent-region (mark)] ["Buffer" vhdl-indent-buffer t]) ("Align" ["Group" vhdl-align-group t] ["Region" vhdl-align-noindent-region (mark)] ["Buffer" vhdl-align-noindent-buffer t] "--" ["Inline Comment Group" vhdl-align-inline-comment-group t] ["Inline Comment Region" vhdl-align-inline-comment-region (mark)] ["Inline Comment Buffer" vhdl-align-inline-comment-buffer t] "--" ["Fixup Whitespace Region" vhdl-fixup-whitespace-region (mark)] ["Fixup Whitespace Buffer" vhdl-fixup-whitespace-buffer t]) ("Fix Case" ["Region" vhdl-fix-case-region (mark)] ["Buffer" vhdl-fix-case-buffer t]) ("Beautify" ["Beautify Region" vhdl-beautify-region (mark)] ["Beautify Buffer" vhdl-beautify-buffer t]) ["Fontify Buffer" vhdl-fontify-buffer t] ["Syntactic Info" vhdl-show-syntactic-information t] ("Documentation" ["VHDL Mode" vhdl-doc-mode :keys "C-c C-h"] ["Reserved Words" (vhdl-doc-variable 'vhdl-doc-keywords) t] ["Coding Style" (vhdl-doc-variable 'vhdl-doc-coding-style) t]) ["Version" vhdl-version t] ["Bug Report..." vhdl-submit-bug-report t] ("Speedbar" ["Open/Close" vhdl-speedbar t] "--" ["Show Hierarchy" vhdl-speedbar-toggle-hierarchy :style toggle :selected (and (boundp 'speedbar-initial-expansion-list-name) (equal speedbar-initial-expansion-list-name "vhdl hierarchy")) :active (and (boundp 'speedbar-frame) speedbar-frame)]) ("Customize" ["Browse VHDL Group..." vhdl-customize t] ["Build Customize Menu" vhdl-create-customize-menu (fboundp 'customize-menu-create)] "--" ["Activate New Customizations" vhdl-activate-customizations t]) standard vhdl-standard x vhdl-model-alist model model-alist] 31 (#$ . 72007)]) #@17 VHDL Mode menu. (defvar vhdl-mode-menu-list (vhdl-create-mode-menu) (#$ . 81306)) #@24 Update VHDL mode menu. (defalias 'vhdl-update-mode-menu #[nil "\303!\210\304 \305!\210\306\301\307\310#\210\311\301!\204�\312\313\301\n\310$\207" [vhdl-mode-menu-list vhdl-mode-menu vhdl-mode-map easy-menu-remove vhdl-create-mode-menu easy-menu-add put variable-documentation "Menu keymap for VHDL Mode." boundp nil easy-menu-do-define] 5 (#$ . 81394) nil]) (require 'easymenu) #@74 Imenu generic expression for VHDL Mode. See `imenu-generic-expression'. (defvar vhdl-imenu-generic-expression '(("Subprogram" "^\\s-*\\(\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\s-+\\(\"?\\(\\w\\|\\s_\\)+\"?\\)" 4) ("Instance" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\s-*:\\(\\s-\\|\n\\)*\\(\\w\\|\\s_\\)+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>" 1) ("Component" "^\\s-*\\(component\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2) ("Procedural" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(procedural\\)" 1) ("Process" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(\\(postponed\\s-+\\|\\)process\\)" 1) ("Block" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(block\\)" 1) ("Package" "^\\s-*\\(package\\( body\\|\\)\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 3) ("Configuration" "^\\s-*\\(configuration\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Architecture" "^\\s-*\\(architecture\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Entity" "^\\s-*\\(entity\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2)) (#$ . 81784)) #@24 Initialize index menu. (defalias 'vhdl-index-menu-init #[nil "\304\305!\306L\210\304\307!L\210 \205,�\310\311\n\"?\205,�\312\303!\203%� \313 V\203)�\314\315!\207\316\317!\207" [vhdl-imenu-generic-expression vhdl-index-menu emacs-version font-lock-maximum-size make-local-variable imenu-case-fold-search t imenu-generic-expression string-match "XEmacs" boundp buffer-size imenu-add-to-menubar "Index" message "Scanning buffer for index...buffer too big"] 3 (#$ . 82854)]) (byte-code "\301B\302\301!\204\f�\303\303\207" [current-load-list vhdl-sources-menu boundp nil] 2) #@79 Call `directory-files' if DIRECTORY exists, otherwise generate error message. (defalias 'vhdl-directory-files #[(directory &optional full match) "\303!\203\f�\304 \n#\207\305\306\"\210\307\207" [directory full match file-directory-p directory-files message "No such directory: \"%s\"" nil] 4 (#$ . 83434)]) #@66 Get list of VHDL source files in DIRECTORY or current directory. (defalias 'vhdl-get-source-files #[(&optional full directory) "\306\307\n\203 �\n@A\310=\203� \n@@\311Q\nA\211\204\n� \312\313\314 \"O\315P\316 \2060�\f #\237*\207" [auto-mode-alist filename-regexp mode-alist directory default-directory full nil ".*\\(" vhdl-mode "\\|" 0 string-match "\\\\|$" "\\)" vhdl-directory-files] 6 (#$ . 83750)]) #@114 Scan directory for all VHDL source files and generate menu. The directory of the current source file is scanned. (defalias 'vhdl-add-source-files-menu #[nil "\306\307!\210\310 \311 \312\211\312 \203+�\313\314 @\315 @D\313#\nB A\211\204�\316\n\317\" \2038�\320\nB\321\nB\322\nB\323\n!\210\324\325\326\327#\210\330\325!\204S�\312\331\325 \327\n$\210-\306\332!\207" [auto-mode-alist found menu-list file-list mode-alist newmap message "Scanning directory for source files ..." current-local-map vhdl-get-source-files nil t vector find-file vhdl-menu-split 25 "--" ["*Rescan*" vhdl-add-source-files-menu t] "Sources" easy-menu-add put vhdl-sources-menu variable-documentation "VHDL source files menu" boundp easy-menu-do-define ""] 6 (#$ . 84170) nil]) #@68 Split menu LIST into several submenues, if number of elements > N. (defalias 'vhdl-menu-split #[(list n) "G V\203Q�\306\211\307\310  \203?� @\fB A \nT\211 U\203�\311\312 \"\f\237B B\310 T\306\202�\f\203M�\311\312 \"\f\237B B \237-\207\207" [list n i menuno sublist result nil 1 0 format "Sources %s" remain] 6 (#$ . 84942)]) #@15003 Major mode for editing VHDL code. Usage: ------ - TEMPLATE INSERTION (electrification): After typing a VHDL keyword and entering `\[vhdl-electric-space]', you are prompted for arguments while a template is generated for that VHDL construct. Typing `\[vhdl-electric-return]' or `\[keyboard-quit]' at the first (mandatory) prompt aborts the current template generation. Optional arguments are indicated by square brackets and removed if the queried string is left empty. Prompts for mandatory arguments remain in the code if the queried string is left empty. They can be queried again by `\[vhdl-template-search-prompt]'. Typing `\[just-one-space]' after a keyword inserts a space without calling the template generator. Automatic template generation (i.e. electrification) can be disabled (enabled) by typing `\[vhdl-electric-mode]' or by setting custom variable `vhdl-electric-mode' (see CUSTOMIZATION). Enabled electrification is indicated by `/e' in the modeline. Template generators can be invoked from the VHDL menu, by key bindings, by typing `C-c C-i C-c' and choosing a construct, or by typing the keyword (i.e. first word of menu entry not in parenthesis) and `\[vhdl-electric-space]'. The following abbreviations can also be used: arch, attr, cond, conf, comp, cons, func, inst, pack, sig, var. Template styles can be customized in customization group `vhdl-electric' (see CUSTOMIZATION). - HEADER INSERTION: A file header can be inserted by `\[vhdl-template-header]'. A file footer (template at the end of the file) can be inserted by `\[vhdl-template-footer]'. See customization group `vhdl-header'. - STUTTERING: Double striking of some keys inserts cumbersome VHDL syntax elements. Stuttering can be disabled (enabled) by typing `\[vhdl-stutter-mode]' or by variable `vhdl-stutter-mode'. Enabled stuttering is indicated by `/s' in the modeline. The stuttering keys and their effects are: ;; --> " : " [ --> ( -- --> comment ;;; --> " := " [[ --> [ --CR --> comment-out code .. --> " => " ] --> ) --- --> horizontal line ,, --> " <= " ]] --> ] ---- --> display comment == --> " == " '' --> \" - WORD COMPLETION: Typing `\[vhdl-electric-tab]' after a (not completed) word looks for a VHDL keyword or a word in the buffer that starts alike, inserts it and adjusts case. Re-typing `\[vhdl-electric-tab]' toggles through alternative word completions. This also works in the minibuffer (i.e. in template generator prompts). Typing `\[vhdl-electric-tab]' after `(' looks for and inserts complete parenthesized expressions (e.g. for array index ranges). All keywords as well as standard types and subprograms of VHDL have predefined abbreviations (e.g. type "std" and `\[vhdl-electric-tab]' will toggle through all standard types beginning with "std"). Typing `\[vhdl-electric-tab]' after a non-word character indents the line if at the beginning of a line (i.e. no preceding non-blank characters),and inserts a tabulator stop otherwise. `\[tab-to-tab-stop]' always inserts a tabulator stop. - COMMENTS: `--' puts a single comment. `---' draws a horizontal line for separating code segments. `----' inserts a display comment, i.e. two horizontal lines with a comment in between. `--CR' comments out code on that line. Re-hitting CR comments out following lines. `\[vhdl-comment-uncomment-region]' comments out a region if not commented out, uncomments a region if already commented out. You are prompted for comments after object definitions (i.e. signals, variables, constants, ports) and after subprogram and process specifications if variable `vhdl-prompt-for-comments' is non-nil. Comments are automatically inserted as additional labels (e.g. after begin statements) and as help comments if `vhdl-self-insert-comments' is non-nil. Inline comments (i.e. comments after a piece of code on the same line) are indented at least to `vhdl-inline-comment-column'. Comments go at maximum to `vhdl-end-comment-column'. `\[vhdl-electric-return]' after a space in a comment will open a new comment line. Typing beyond `vhdl-end-comment-column' in a comment automatically opens a new comment line. `\[fill-paragraph]' re-fills multi-line comments. - INDENTATION: `\[vhdl-electric-tab]' indents a line if at the beginning of the line. The amount of indentation is specified by variable `vhdl-basic-offset'. `\[vhdl-indent-line]' always indents the current line (is bound to `TAB' if variable `vhdl-intelligent-tab' is nil). Indentation can be done for an entire region (`\[vhdl-indent-region]') or buffer (menu). Argument and port lists are indented normally (nil) or relative to the opening parenthesis (non-nil) according to variable `vhdl-argument-list-indent'. If variable `vhdl-indent-tabs-mode' is nil, spaces are used instead of tabs. `\[tabify]' and `\[untabify]' allow to convert spaces to tabs and vice versa. - ALIGNMENT: The alignment functions align operators, keywords, and inline comment to beautify argument lists, port maps, etc. `\[vhdl-align-group]' aligns a group of consecutive lines separated by blank lines. `\[vhdl-align-noindent-region]' aligns an entire region. If variable `vhdl-align-groups' is non-nil, groups of code lines separated by empty lines are aligned individually. `\[vhdl-align-inline-comment-group]' aligns inline comments for a group of lines, and `\[vhdl-align-inline-comment-region]' for a region. Some templates are automatically aligned after generation if custom variable `vhdl-auto-align' is non-nil. `\[vhdl-fixup-whitespace-region]' fixes up whitespace in a region. That is, operator symbols are surrounded by one space, and multiple spaces are eliminated. - PORT TRANSLATION: Generic and port clauses from entity or component declarations can be copied (`\[vhdl-port-copy]') and pasted as entity and component declarations, as component instantiations and corresponding internal constants and signals, as a generic map with constants as actual parameters, and as a test bench (menu). A clause with several generic/port names on the same line can be flattened (`\[vhdl-port-flatten]') so that only one name per line exists. Names for actual ports, instances, test benches, and design-under-test instances can be derived from existing names according to variables `vhdl-...-name'. Variables `vhdl-testbench-...' allow the insertion of additional templates into a test bench. New files are created for the test bench entity and architecture according to variable `vhdl-testbench-create-files'. See customization group `vhdl-port'. - TEST BENCH GENERATION: See PORT TRANSLATION. - KEY BINDINGS: Key bindings (`C-c ...') exist for most commands (see in menu). - VHDL MENU: All commands can be invoked from the VHDL menu. - FILE BROWSER: The speedbar allows browsing of directories and file contents. It can be accessed from the VHDL menu and is automatically opened if variable `vhdl-speedbar' is non-nil. In speedbar, open files and directories with `mouse-2' on the name and browse/rescan their contents with `mouse-2'/`S-mouse-2' on the `+'. - DESIGN HIERARCHY BROWSER: The speedbar can also be used for browsing the hierarchy of design units contained in the source files of the current directory or in the source files/directories specified for a project (see variable `vhdl-project-alist'). The speedbar can be switched between file and hierarchy browsing mode in the VHDL menu or by typing `f' and `h' in speedbar. In speedbar, open design units with `mouse-2' on the name and browse their hierarchy with `mouse-2' on the `+'. The hierarchy can be rescanned and ports directly be copied from entities by using the speedbar menu. - PROJECTS: Projects can be defined in variable `vhdl-project-alist' and a current project be selected using variable `vhdl-project' (permanently) or from the menu (temporarily). For each project, a title string (for the file headers) and source files/directories (for the hierarchy browser) can be specified. - SPECIAL MENUES: As an alternative to the speedbar, an index menu can be added (set variable `vhdl-index-menu' to non-nil) or made accessible as a mouse menu (e.g. add "(global-set-key '[S-down-mouse-3] 'imenu)" to your start-up file) for browsing the file contents. Also, a source file menu can be added (set variable `vhdl-source-file-menu' to non-nil) for browsing the current directory for VHDL source files. - SOURCE FILE COMPILATION: The syntax of the current buffer can be analyzed by calling a VHDL compiler (menu, `\[vhdl-compile]'). The compiler to be used is specified by variable `vhdl-compiler'. The available compilers are listed in variable `vhdl-compiler-alist' including all required compilation command, destination directory, and error message syntax information. New compilers can be added. Additional compile command options can be set in variable `vhdl-compiler-options'. An entire hierarchy of source files can be compiled by the `make' command (menu, `\[vhdl-make]'). This only works if an appropriate Makefile exists. The make command itself as well as a command to generate a Makefile can also be specified in variable `vhdl-compiler-alist'. - VHDL STANDARDS: The VHDL standards to be used are specified in variable `vhdl-standard'. Available standards are: VHDL'87/'93, VHDL-AMS, Math Packages. - KEYWORD CASE: Lower and upper case for keywords and standardized types, attributes, and enumeration values is supported. If the variable `vhdl-upper-case-keywords' is set to non-nil, keywords can be typed in lower case and are converted into upper case automatically (not for types, attributes, and enumeration values). The case of keywords, types, attributes,and enumeration values can be fixed for an entire region (menu) or buffer (`\[vhdl-fix-case-buffer]') according to the variables `vhdl-upper-case-{keywords,types,attributes,enum-values}'. - HIGHLIGHTING (fontification): Keywords and standardized types, attributes, enumeration values, and function names (controlled by variable `vhdl-highlight-keywords'), as well as comments, strings, and template prompts are highlighted using different colors. Unit, subprogram, signal, variable, constant, parameter and generic/port names in declarations as well as labels are highlighted if variable `vhdl-highlight-names' is non-nil. Additional reserved words or words with a forbidden syntax (e.g. words that should be avoided) can be specified in variable `vhdl-forbidden-words' or `vhdl-forbidden-syntax' and be highlighted in a warning color (variable `vhdl-highlight-forbidden-words'). Verilog keywords are highlighted as forbidden words if variable `vhdl-highlight-verilog-keywords' is non-nil. Words with special syntax can be highlighted by specifying their syntax and color in variable `vhdl-special-syntax-alist' and by setting variable `vhdl-highlight-special-words' to non-nil. This allows to establish some naming conventions (e.g. to distinguish different kinds of signals or other objects by using name suffices) and to support them visually. Variable `vhdl-highlight-case-sensitive' can be set to non-nil in order to support case-sensitive highlighting. However, keywords are then only highlighted if written in lower case. Code between "translate_off" and "translate_on" pragmas is highlighted using a different background color if variable `vhdl-highlight-translate-off' is non-nil. All colors can be customized by command `\[customize-face]'. For highlighting of matching parenthesis, see customization group `paren-showing' (`\[customize-group]'). - USER MODELS: VHDL models (templates) can be specified by the user and made accessible in the menu, through key bindings (`C-c C-m ...'), or by keyword electrification. See custom variable `vhdl-model-alist'. - HIDE/SHOW: The code of entire VHDL design units can be hidden using the `Hide/Show' menu or by pressing `S-mouse-2' within the code (variable `vhdl-hideshow-menu'). - PRINTING: Postscript printing with different faces (an optimized set of faces is used if `vhdl-print-customize-faces' is non-nil) or colors (if `ps-print-color-p' is non-nil) is possible using the standard Emacs postscript printing commands. Variable `vhdl-print-two-column' defines appropriate default settings for nice landscape two-column printing. The paper format can be set by variable `ps-paper-type'. Do not forget to switch `ps-print-color-p' to nil for printing on black-and-white printers. - CUSTOMIZATION: All variables can easily be customized using the `Customize' menu entry or `\[customize-option]' (`\[customize-group]' for groups). Some customizations only take effect after some action (read the NOTE in the variable documentation). Customization can also be done globally (i.e. site-wide, read the INSTALL file). - FILE EXTENSIONS: As default, files with extensions ".vhd" and ".vhdl" are automatically recognized as VHDL source files. To add an extension ".xxx", add the following line to your Emacs start-up file (`.emacs'): (setq auto-mode-alist (cons '("\\.xxx\\'" . vhdl-mode) auto-mode-alist)) - HINTS: - Type `\[keyboard-quit] \[keyboard-quit]' to interrupt long operations or if Emacs hangs. Maintenance: ------------ To submit a bug report, enter `\[vhdl-submit-bug-report]' within VHDL Mode. Add a description of the problem and include a reproducible test case. Questions and enhancement requests can be sent to <vhdl-mode@geocities.com>. The `vhdl-mode-announce' mailing list informs about new VHDL Mode releases. The `vhdl-mode-victims' mailing list informs about new VHDL Mode beta releases. You are kindly invited to participate in beta testing. Subscribe to above mailing lists by sending an email to <vhdl-mode@geocities.com>. VHDL Mode is officially distributed on the Emacs VHDL Mode Home Page <http://www.geocities.com/SiliconValley/Peaks/8287>, where the latest version and release notes can be found. Bugs and Limitations: --------------------- - Re-indenting large regions or expressions can be slow. - Indentation bug in simultaneous if- and case-statements (VHDL-AMS). - Hideshow does not work under XEmacs. - Index menu and file tagging in speedbar do not work under XEmacs. - Parsing compilation error messages for Ikos and Viewlogic VHDL compilers does not work under XEmacs. The VHDL Mode Maintainers Reto Zimmermann and Rod Whitby Key bindings: ------------- \{vhdl-mode-map} (defalias 'vhdl-mode #[nil "\306 \210\307\310\311\n!\210\312 !\210\f\313\314!\315L\210\313\316!\fL\210\313\317!\320L\210\313\321!\320L\210\313\322!\320L\210\313\323!\324L\210\313\325!\326L\210\313\327!\330L\210\313\331!@L\210\313\332!AL\210\313\333!\334L\210\313\335!\336L\210\313\337!BL\210\313\340!\341L\210\313\342!\336L\210\343\344!\203|�\313\344!\210\345$\346\347!\210\313\350!\351\336C?\352\353\354\257L\210\313\355!\356L\210\313\357!\336L\210\313\360!\320L\210\313\361!\320L\210\362 \210\346\363!\210\313\364!\336L\210\313\365!\336L\210\366 \210D\203\305�\367 \210\370E!\210\371\372\373\374#\210\343\372!\204\331�\336:\375\372\n\374E$\210\313\376!\210\377 \210\201G�\201H�!\210\201I�\201J�!\203\336\201K�\201L�\217\210\201M� \210\201N� \210\201O� \210\201P�\201Q�F\"\210\201R� \210\201G�\201S�!\207" [major-mode mode-name vhdl-mode-map vhdl-mode-syntax-table vhdl-mode-abbrev-table local-abbrev-table kill-all-local-variables vhdl-mode "VHDL" use-local-map set-syntax-table make-local-variable paragraph-start "\\s-*\\(--+\\s-*$\\|[^ -]\\|$\\)" paragraph-separate paragraph-ignore-fill-prefix t require-final-newline parse-sexp-ignore-comments indent-line-function vhdl-indent-line comment-start "--" comment-end "" comment-column end-comment-column comment-start-skip "--+\\s-*" comment-multi-line nil indent-tabs-mode hippie-expand-only-buffers (vhdl-mode) hippie-expand-verbose boundp comment-indent-function vhdl-comment-indent require font-lock font-lock-defaults vhdl-font-lock-keywords ((95 . "w")) beginning-of-line (font-lock-syntactic-keywords . vhdl-font-lock-syntactic-keywords) font-lock-support-mode lazy-lock-mode lazy-lock-defer-contextually lazy-lock-defer-on-the-fly lazy-lock-defer-on-scrolling turn-on-font-lock compile compilation-error-regexp-alist compilation-file-regexp-alist vhdl-index-menu-init vhdl-add-source-files-menu easy-menu-add put vhdl-mode-menu variable-documentation "Menu keymap for VHDL Mode." easy-menu-do-define hs-minor-mode-hook vhdl-hideshow-init vhdl-inline-comment-column vhdl-end-comment-column vhdl-indent-tabs-mode vhdl-highlight-case-sensitive vhdl-source-file-menu vhdl-mode-menu-list vhdl-version run-hooks menu-bar-update-hook fboundp speedbar (byte-code "\203�\303\301!\203�\304 !\204�\305\306!\210\307\n!\210\303\207" [vhdl-speedbar speedbar-frame speedbar-attached-frame boundp frame-live-p speedbar-frame-mode 1 select-frame] 2) ((error (vhdl-add-warning "Before using Speedbar, install included `speedbar.el' patch"))) vhdl-ps-print-init vhdl-modify-date-init vhdl-mode-line-update message "VHDL Mode %s. Type C-c C-h for documentation." vhdl-print-warnings vhdl-mode-hook] 7 (#$ . 85297) nil]) #@49 Activate all customizations on local variables. (defalias 'vhdl-activate-customizations #[nil "\306 \210\307!\210\310 !\210\n\f\311 \210\312 \210\313 \210\314\315!\210\316 \207" [vhdl-mode-map vhdl-mode-syntax-table vhdl-inline-comment-column comment-column vhdl-end-comment-column end-comment-column vhdl-mode-map-init use-local-map set-syntax-table vhdl-modify-date-init vhdl-update-mode-menu vhdl-hideshow-init run-hooks menu-bar-update-hook vhdl-mode-line-update] 2 (#$ . 102988) nil]) #@58 Add/remove hook for modifying date when buffer is saved. (defalias 'vhdl-modify-date-init #[nil "\203 �\301\302\303\"\207\304\302\303\"\207" [vhdl-modify-date-on-saving add-hook local-write-file-hooks vhdl-template-modify-noerror remove-hook] 3 (#$ . 103487)]) #@1009 Reserved words in VHDL: VHDL'93 (IEEE Std 1076-1993): `vhdl-93-keywords' : keywords `vhdl-93-types' : standardized types `vhdl-93-attributes' : standardized attributes `vhdl-93-enum-values' : standardized enumeration values `vhdl-93-functions' : standardized functions `vhdl-93-packages' : standardized packages and libraries VHDL-AMS (IEEE Std 1076.1): `vhdl-ams-keywords' : keywords `vhdl-ams-types' : standardized types `vhdl-ams-attributes' : standardized attributes `vhdl-ams-enum-values' : standardized enumeration values `vhdl-ams-functions' : standardized functions Math Packages (IEEE Std 1076.2): `vhdl-math-types' : standardized types `vhdl-math-constants' : standardized constants `vhdl-math-functions' : standardized functions `vhdl-math-packages' : standardized packages Forbidden words: `vhdl-verilog-keywords' : Verilog reserved words NOTE: click `mouse-2' on variable names above (not in XEmacs). (defvar vhdl-doc-keywords nil (#$ . 103757)) #@630 For VHDL coding style and naming convention guidelines, see the following references: [1] Ben Cohen. "VHDL Coding Styles and Methodologies". Kluwer Academic Publishers, 1999. http://members.aol.com/vhdlcohen/vhdl/ [2] Michael Keating and Pierre Bricaud. "Reuse Methodology Manual". Kluwer Academic Publishers, 1998. http://www.synopsys.com/products/reuse/rmm.html [3] European Space Agency. "VHDL Modelling Guidelines". ftp://ftp.estec.esa.nl/pub/vhdl/doc/ModelGuide.{pdf,ps} Use variables `vhdl-highlight-special-words' and `vhdl-special-syntax-alist' to visually support naming conventions. (defvar vhdl-doc-coding-style nil (#$ . 104817)) #@52 Display VARIABLE's documentation in *Help* buffer. (defalias 'vhdl-doc-variable #[(variable) "\303\220\304\305\306\"!\210\307\310 \"\204�\311\312Dt\"\210\212\nq\210\313 \210)\314 \221\207" [variable emacs-version standard-output "*Help*" princ documentation-property variable-documentation string-match "XEmacs" help-setup-xref vhdl-doc-variable help-mode print-help-return-message] 5 (#$ . 105501) nil]) #@51 Display VHDL mode documentation in *Help* buffer. (defalias 'vhdl-doc-mode #[nil "\303\220\304!\210\304\305!\210\304\306\307!!\210\310\311 \"\204�\312\313Ct\"\210\212\nq\210\314 \210)\315 \221\207" [mode-name emacs-version standard-output "*Help*" princ " mode:\n" documentation vhdl-mode string-match "XEmacs" help-setup-xref vhdl-doc-mode help-mode print-help-return-message] 4 (#$ . 105915) nil]) #@27 List of VHDL'93 keywords. (defconst vhdl-93-keywords '("abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "shared" "signal" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor") (#$ . 106323)) #@28 List of VHDL-AMS keywords. (defconst vhdl-ams-keywords '("across" "break" "limit" "nature" "noise" "procedural" "quantity" "reference" "spectrum" "subnature" "terminal" "through" "tolerance") (#$ . 107191)) #@70 List of Verilog keywords as candidate for additional reserved words. (defconst vhdl-verilog-keywords '("`define" "`else" "`endif" "`ifdef" "`include" "`timescale" "`undef" "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cmos" "deassign" "default" "defparam" "disable" "edge" "else" "end" "endattribute" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" "large" "macromodule" "makefile" "medium" "module" "nand" "negedge" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pulldown" "pullup" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "signed" "small" "specify" "specparam" "strength" "strong0" "strong1" "supply" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xnor" "xor") (#$ . 107404)) #@37 List of VHDL'93 standardized types. (defconst vhdl-93-types '("boolean" "bit" "bit_vector" "character" "severity_level" "integer" "real" "time" "natural" "positive" "string" "line" "text" "side" "unsigned" "signed" "delay_length" "file_open_kind" "file_open_status" "std_logic" "std_logic_vector" "std_ulogic" "std_ulogic_vector") (#$ . 108535)) #@38 List of VHDL-AMS standardized types. (defconst vhdl-ams-types '("domain_type" "real_vector") (#$ . 108887)) #@43 List of Math Packages standardized types. (defconst vhdl-math-types '("complex" "complex_polar") (#$ . 109001)) #@42 List of VHDL'93 standardized attributes. (defconst vhdl-93-attributes '("base" "left" "right" "high" "low" "pos" "val" "succ" "pred" "leftof" "rightof" "range" "reverse_range" "length" "delayed" "stable" "quiet" "transaction" "event" "active" "last_event" "last_active" "last_value" "driving" "driving_value" "ascending" "value" "image" "simple_name" "instance_name" "path_name" "foreign") (#$ . 109119)) #@43 List of VHDL-AMS standardized attributes. (defconst vhdl-ams-attributes '("across" "through" "reference" "contribution" "tolerance" "dot" "integ" "delayed" "above" "zoh" "ltf" "ztf" "ramp" "slew") (#$ . 109530)) #@50 List of VHDL'93 standardized enumeration values. (defconst vhdl-93-enum-values '("true" "false" "note" "warning" "error" "failure" "read_mode" "write_mode" "append_mode" "open_ok" "status_error" "name_error" "mode_error" "fs" "ps" "ns" "us" "ms" "sec" "min" "hr" "right" "left") (#$ . 109748)) #@51 List of VHDL-AMS standardized enumeration values. (defconst vhdl-ams-enum-values '("quiescent_domain" "time_domain" "frequency_domain") (#$ . 110048)) #@47 List of Math Packages standardized constants. (defconst vhdl-math-constants '("math_e" "math_1_over_e" "math_pi" "math_two_pi" "math_1_over_pi" "math_half_pi" "math_q_pi" "math_3_half_pi" "math_log_of_2" "math_log_of_10" "math_log2_of_e" "math_log10_of_e" "math_sqrt2" "math_sqrt1_2" "math_sqrt_pi" "math_deg_to_rad" "math_rad_to_deg" "cbase_1" "cbase_j" "czero") (#$ . 110205)) #@41 List of VHDL'93 standardized functions. (defconst vhdl-93-functions '("now" "resolved" "rising_edge" "falling_edge" "read" "readline" "write" "writeline" "endfile" "resize" "is_X" "std_match" "shift_left" "shift_right" "rotate_left" "rotate_right" "to_unsigned" "to_signed" "to_integer" "to_stdLogicVector" "to_stdULogic" "to_stdULogicVector" "to_bit" "to_bitVector" "to_X01" "to_X01Z" "to_UX01" "to_01" "conv_unsigned" "conv_signed" "conv_integer" "conv_std_logic_vector" "shl" "shr" "ext" "sxt") (#$ . 110590)) #@42 List of VHDL-AMS standardized functions. (defconst vhdl-ams-functions '("frequency") (#$ . 111109)) #@47 List of Math Packages standardized functions. (defconst vhdl-math-functions '("sign" "ceil" "floor" "round" "trunc" "fmax" "fmin" "uniform" "sqrt" "cbrt" "exp" "log" "sin" "cos" "tan" "arcsin" "arccos" "arctan" "sinh" "cosh" "tanh" "arcsinh" "arccosh" "arctanh" "cmplx" "complex_to_polar" "polar_to_complex" "arg" "conj") (#$ . 111215)) #@54 List of VHDL'93 standardized packages and libraries. (defconst vhdl-93-packages '("std_logic_1164" "numeric_std" "numeric_bit" "standard" "textio" "std_logic_arith" "std_logic_signed" "std_logic_unsigned" "std_logic_misc" "std_logic_textio" "ieee" "std" "work") (#$ . 111558)) #@60 List of Math Packages standardized packages and libraries. (defconst vhdl-math-packages '("math_real" "math_complex") (#$ . 111841)) #@24 List of VHDL keywords. (defvar vhdl-keywords nil (#$ . 111980)) #@34 List of VHDL standardized types. (defvar vhdl-types nil (#$ . 112050)) #@39 List of VHDL standardized attributes. (defvar vhdl-attributes nil (#$ . 112127)) #@47 List of VHDL standardized enumeration values. (defvar vhdl-enum-values nil (#$ . 112214)) #@38 List of VHDL standardized constants. (defvar vhdl-constants nil (#$ . 112310)) #@38 List of VHDL standardized functions. (defvar vhdl-functions nil (#$ . 112395)) #@51 List of VHDL standardized packages and libraries. (defvar vhdl-packages nil (#$ . 112480)) #@36 List of additional reserved words. (defvar vhdl-reserved-words nil (#$ . 112577)) #@27 Regexp for VHDL keywords. (defvar vhdl-keywords-regexp nil (#$ . 112665)) #@37 Regexp for VHDL standardized types. (defvar vhdl-types-regexp nil (#$ . 112745)) #@42 Regexp for VHDL standardized attributes. (defvar vhdl-attributes-regexp nil (#$ . 112832)) #@50 Regexp for VHDL standardized enumeration values. (defvar vhdl-enum-values-regexp nil (#$ . 112929)) #@41 Regexp for VHDL standardized functions. (defvar vhdl-functions-regexp nil (#$ . 113035)) #@54 Regexp for VHDL standardized packages and libraries. (defvar vhdl-packages-regexp nil (#$ . 113130)) #@39 Regexp for additional reserved words. (defvar vhdl-reserved-words-regexp nil (#$ . 113237)) #@28 Initialize reserved words. (defalias 'vhdl-words-init #[nil "\306\307\307\n@=\206� \n\211A@)>)\205�\f\"\306\307\307\n@=\206.� \n\211A@)>)\2054�\310\310\n@=\206E� \n\211A@)>)\205K�#\306\307\307\n@=\206b� \n\211A@)>)\205h�\"\306\307\307\n@=\206� \n\211A@)>)\205\205�\"\306\310\310\n@=\206\232� \n\211A@)>)\205\240�!\306\307\307\n@=\206\267� \n\211A@)>)\205\275�\310\310\n@=\206\316� \n\211A@)>)\205\324�#\306 \310\310\n@=\206\353� \n\211A@)>)\205\361�!\"\"\306#\205\374�$%\205&\311#'\312\313 !\314Q(\312\313!\314Q)\312\313!\314Q*\312\313!\314Q+\312\313!\314Q,\312\313\"!\314Q-\312.\315\232?\205I.\316P\313'!\314R/\317 \207" [vhdl-93-keywords standard vhdl-standard x vhdl-ams-keywords vhdl-keywords append ams math ("") "\\<\\(" regexp-opt "\\)\\>" "" "\\|" vhdl-abbrev-list-init vhdl-93-types vhdl-ams-types vhdl-math-types vhdl-types vhdl-93-attributes vhdl-ams-attributes vhdl-attributes vhdl-93-enum-values vhdl-ams-enum-values vhdl-enum-values vhdl-math-constants vhdl-constants vhdl-93-functions vhdl-ams-functions vhdl-math-functions vhdl-functions vhdl-93-packages vhdl-math-packages vhdl-packages vhdl-highlight-forbidden-words vhdl-forbidden-words vhdl-highlight-verilog-keywords vhdl-verilog-keywords vhdl-reserved-words vhdl-keywords-regexp vhdl-types-regexp vhdl-attributes-regexp vhdl-enum-values-regexp vhdl-functions-regexp vhdl-packages-regexp vhdl-forbidden-syntax vhdl-reserved-words-regexp] 6 (#$ . 113335)]) #@36 Predefined abbreviations for VHDL. (defvar vhdl-abbrev-list nil (#$ . 114853)) (defalias 'vhdl-abbrev-list-init #[nil "\306C \nC \fC C \nC \307C\f\307C &\211\207" [vhdl-upper-case-keywords vhdl-keywords vhdl-upper-case-types vhdl-types vhdl-upper-case-attributes vhdl-attributes append nil vhdl-upper-case-enum-values vhdl-enum-values vhdl-upper-case-constants vhdl-constants vhdl-functions vhdl-packages vhdl-abbrev-list] 15]) (vhdl-words-init) #@210 Regexp describing a VHDL symbol. We cannot use just `word' syntax class since `_' cannot be in word class. Putting underscore in word class breaks forward word movement behavior that users are familiar with. (defconst vhdl-symbol-key "\\(\\w\\|\\s_\\)+" (#$ . 115317)) #@48 Regexp describing a case statement header key. (defconst vhdl-case-header-key "case[( \n][^;=>]+[) \n]is" (#$ . 115593)) #@33 Regexp describing a VHDL label. (defconst vhdl-label-key (concat "\\(" vhdl-symbol-key "\\s-*:\\)[^=]") (#$ . 115722)) #@431 Return the value of point at certain commonly referenced POSITIONs. POSITION can be one of the following symbols: bol -- beginning of line eol -- end of line bod -- beginning of defun boi -- back to indentation eoi -- last whitespace on line ionl -- indentation of next line iopl -- indentation of previous line bonl -- beginning of next line bopl -- beginning of previous line This function does not modify point or mark. (defalias 'vhdl-point '(macro . #[(position) "\301\242=\203 �AA\203�\302\303\"\210A@\304\305\306\307=\203#�\310\202w�\311=\203-�\312\202w�\313=\2037�\314\202w�\315=\203A�\316\202w�\317=\203K�\320\202w�\321=\203U�\322\202w�\323=\203_�\324\202w�\325=\203i�\326\202w�\327=\203s�\330\202w�\302\331\"\332\333#BB\207" [position quote error "Bad buffer position requested: %s" let ((here (point))) append bol ((beginning-of-line)) eol ((end-of-line)) bod ((save-match-data (vhdl-beginning-of-defun))) boi ((back-to-indentation)) eoi ((end-of-line) (skip-chars-backward " ")) bonl ((forward-line 1)) bopl ((forward-line -1)) iopl ((forward-line -1) (back-to-indentation)) ionl ((forward-line 1) (back-to-indentation)) "Unknown buffer position requested: %s" ((prog1 (point) (goto-char here))) nil] 6 (#$ . 115848)])) #@55 Safely execute BODY, return nil if an error occurred. (defalias 'vhdl-safe '(macro . #[(&rest body) "\301\302\303B\304BBB\207" [body condition-case nil progn ((error nil))] 4 (#$ . 117110)])) #@116 A simple macro to append the syntax in SYMBOL to the syntax list. Try to increase performance by using this macro. (defalias 'vhdl-add-syntax '(macro . #[(symbol &optional relpos) "\302\303\304\211 E\305BBE\207" [symbol relpos setq vhdl-syntactic-context cons (vhdl-syntactic-context)] 6 (#$ . 117310)])) #@98 A simple macro to return check the syntax list. Try to increase performance by using this macro. (defalias 'vhdl-has-syntax '(macro . #[(symbol) "\301\302BB\207" [symbol assoc (vhdl-syntactic-context)] 3 (#$ . 117622)])) #@80 Read new offset value for LANGELEM from minibuffer. Return a legal value only. (defalias 'vhdl-read-offset #[(langelem) "\306\307 \236\243\"\310\311\312\211\211\f\204w�\313 \"\211\314\230\203(�\315\202r� \316\230\2032�\317\202r� \320\230\203<�\321\202r� \322\230\203F�\323\202r�\324\325 \"\203S�\326 !\202r�\327\330 !\211!\203a�\n\202r�\331\n!\203k�\n\202r�\332 \210\312\211\203�\f.\207" [langelem vhdl-offsets-alist interned input offset prompt format "%s" "Offset must be int, func, var, or one of +, -, ++, --: " "Offset: " nil read-string "+" + "-" - "++" ++ "--" -- string-match "^-?[0-9]+$" string-to-int fboundp intern boundp ding errmsg oldoff] 7 (#$ . 117850)]) #@272 Change the value of a syntactic element symbol in `vhdl-offsets-alist'. SYMBOL is the syntactic element symbol to change and OFFSET is the new offset for that syntactic element. Optional ADD says to add SYMBOL to `vhdl-offsets-alist' if it doesn't already appear there. (defalias 'vhdl-set-offset #[(symbol offset &optional add-p) "\305=\204.�\306=\204.�\307=\204.�\310=\204.�\250\204.�\311!\204.�\312!\204.�\313\314\"\210 \n\236\211\203=� \241\210\202O�\f\203J� B\nB\202O�\313\315 \"\210)\316 \207" [offset symbol vhdl-offsets-alist entry add-p + - ++ -- fboundp boundp error "Offset must be int, func, var, or one of +, -, ++, --: %s" "%s is not a valid syntactic symbol" vhdl-keep-region-active] 4 (#$ . 118547) (let* ((langelem (intern (completing-read (concat "Syntactic symbol to change" (if current-prefix-arg " or add" "") ": ") (mapcar #'(lambda (langelem) (cons (format "%s" (car langelem)) nil)) vhdl-offsets-alist) nil (not current-prefix-arg) (let* ((syntax (vhdl-get-syntactic-context)) (len (length syntax)) (ic (format "%s" (car (nth (1- len) syntax))))) ic)))) (offset (vhdl-read-offset langelem))) (list langelem offset current-prefix-arg))]) #@418 Set `vhdl-mode' variables to use one of several different indentation styles. STYLE is a string representing the desired style and optional LOCAL is a flag which, if non-nil, means to make the style variables being changed buffer local, instead of the default, which is to set the global variables. Interactively, the flag comes from the prefix argument. The styles are chosen from the `vhdl-style-alist' variable. (defalias 'vhdl-set-style #[(style &optional local) "\303 \"A\211\204�\304\305\"\210\306\307\n\"\210)\310 \207" [style vhdl-style-alist vars assoc error "Invalid VHDL indentation style `%s'" mapcar #[(varentry) "@A \203�\306\n!\210\n\305=\204�\n L\202\"�\307\f!\310\311 \"*\207" [varentry val var local vhdl-offsets-alist-default vhdl-offsets-alist make-local-variable copy-alist mapcar #[(langentry) "@A\303\n \"*\207" [langentry offset langelem vhdl-set-offset] 3]] 3] vhdl-keep-region-active] 4 (#$ . 119728) (list (completing-read "Use which VHDL indentation style? " vhdl-style-alist nil t) current-prefix-arg)]) #@270 Get offset from LANGELEM which is a cons cell of the form: (SYMBOL . RELPOS). The symbol is matched against vhdl-offsets-alist and the offset found there is either returned, or added to the indentation at RELPOS. If RELPOS is nil, then the offset is simply returned. (defalias 'vhdl-get-offset #[(langelem) "@A \236\211\243\f\204%�\203�\306\307 \"\210\202x�\310\310\202x� \311=\2031�\202x� \312=\203>�[\202x� \313=\203N�\211\\\310\\\202x� \314=\203]�[\315_\202x� \247\204o�\316 !\203o� !\202x� \247\204x�\317 !\n\203\226�\n`\320 \210`b\210)W\203\226�\212\nb\210i)\202\227�\310 \\,\207" [langelem symbol relpos vhdl-offsets-alist match offset error "Don't know how to indent a %s" 0 + - ++ -- 2 fboundp eval beginning-of-line vhdl-strict-syntax-p vhdl-basic-offset here] 4 (#$ . 120785)]) #@42 Determine if point is in a VHDL literal. (defalias 'vhdl-in-literal #[(&optional lim) "\212\302`\303 \210`b\210)`\"\304 8\203�\305\202$�\306 8\203#�\307\202$�\310*\207" [here state parse-partial-sexp beginning-of-line 3 string 4 comment nil] 3 (#$ . 121612)]) #@42 Determine if point is in a VHDL literal. (defalias 'vhdl-win-il #[(&optional lim) "\212`\305\305 \206�`\306 \307\216\310 \210*`b\210)\211b\210`W\203\205�\311\312\313#\2052�\314\224\314\225{\211\204;�\305\202\201�\n\315\230\203N�\305\210`X\205\201�\316\202\201�\n\317\230\203g�\214`}\210\311\320\313#)?\205\201�\321\202\201�\n\322\230\203\200�\214`}\210\311\323\313#)?\205\201�\321\202\201�\305\202� -\207" [here state match lim save-match-data-internal nil match-data ((set-match-data save-match-data-internal)) vhdl-beginning-of-defun re-search-forward "--\\|[\"']" move 0 "--" comment "\"" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)*\"" string "'" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)?'"] 5 (#$ . 121882)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-in-literal vhdl-win-il] 3) #@39 Forward skip of syntactic whitespace. (defalias 'vhdl-forward-syntactic-ws #[(&optional lim) "\214\206�d\211d`}\210 `U?\205�`\303\n!\210\202�,\207" [lim here hugenum forward-comment] 3 (#$ . 122722)]) #@50 Forward skip syntactic whitespace for Win-Emacs. (defalias 'vhdl-win-fsws #[(&optional lim) "\206�d\302 ?\205#�\303w\210\304\305!\203�\302\210\202�\306\211\202 �*\207" [lim stop nil " \n \f" looking-at "--" t] 3 (#$ . 122938)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-forward-syntactic-ws vhdl-win-fsws] 3) #@42 Backward skip over syntactic whitespace. (defalias 'vhdl-backward-syntactic-ws #[(&optional lim) "\214\206�e\211d[`W\205&�`}\210 `U?\205&�`\303\n!\210\202�,\207" [lim here hugenum forward-comment] 3 (#$ . 123318)]) #@51 Backward skip syntactic whitespace for Win-Emacs. (defalias 'vhdl-win-bsws #[(&optional lim) "\206�`\304 \305\216\306 \210*` b\210)\307 ?\205U�\310x\210\311!\312=\203O�\313x\210\314x\210g\315U\203>�`Tf\315U\204�`X\204�\313x\210\314x\210\2020�\316\211\202�*\207" [lim here save-match-data-internal stop match-data ((set-match-data save-match-data-internal)) vhdl-beginning-of-defun nil " \n \f" vhdl-in-literal comment "^-" "-" 45 t] 3 (#$ . 123548)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-backward-syntactic-ws vhdl-win-bsws] 3) #@90 If the keyword at POINT is at boi, then return (current-column) at that point, else nil. (defalias 'vhdl-first-word #[(point) "\212b\205�``\302 \210` b\210)=\205�i)\207" [point here back-to-indentation] 3 (#$ . 124160)]) #@90 If the keyword at POINT is at eoi, then return (current-column) at that point, else nil. (defalias 'vhdl-last-word #[(point) "\212b\205%�\212\302 \210``\303\210\304\303x\210` b\210)=\206 �\305\306!)\205%�i)\207" [point here forward-sexp nil " " looking-at "\\s-*\\(--\\)?"] 3 (#$ . 124391)]) (byte-code "\301B\302\301\207" [current-load-list vhdl-libunit-re "\\b\\(architecture\\|configuration\\|entity\\|package\\)\\b[^_]"] 2) (defalias 'vhdl-libunit-p #[nil "\212\300 \210\301\302w\210\303\304!)?\205&�\212\305 \210\303\306!?\205%�\300 \210\307 \210g\310U?)\207" [forward-sexp " \n" nil looking-at "is\\b[^_]" backward-sexp "use\\b[^_]" vhdl-forward-syntactic-ws 58] 2]) (byte-code "\301B\302\301\207" [current-load-list vhdl-defun-re "\\b\\(architecture\\|block\\|configuration\\|entity\\|package\\|process\\|procedural\\|procedure\\|function\\)\\b[^_]"] 2) (defalias 'vhdl-defun-p #[nil "\212\300\301!\203�\212\302 \210\300\303!)?\202�\304)\207" [looking-at "block\\|process\\|procedural" backward-sexp "end\\s-+\\w" t] 2]) #@169 If the word at the current position corresponds to a "defun" keyword, then return a string that can be used to find the corresponding "begin" keyword, else return nil. (defalias 'vhdl-corresponding-defun #[nil "\212\301!\205�\302 \205�\301\303!\203�\304\224\304\225{\202�\305)\207" [vhdl-defun-re looking-at vhdl-defun-p "block\\|process\\|procedural" 0 "is"] 2 (#$ . 125439)]) #@85 A regular expression for searching forward that matches all known "begin" keywords. (defconst vhdl-begin-fwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\|units\\|record\\|for\\)\\b\\([^_]\\|\\'\\)" (#$ . 125828)) #@86 A regular expression for searching backward that matches all known "begin" keywords. (defconst vhdl-begin-bwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\|units\\|record\\|for\\)\\b[^_]" (#$ . 126100)) #@265 Return t if we are looking at a real "begin" keyword. Assumes that the caller will make sure that we are looking at vhdl-begin-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "begin" keyword. (defalias 'vhdl-begin-p #[(&optional lim) "\303\304!\203B�\212\305 \210\306\2040�\307\310 \311#\2030�h\312U\204$�\313 !\203*�\314u\210\202\f�\315\211\203�)g\316U?\205<�\303\317!?)\203B�\315\207\303\320!\203J�\315\207\303\321!\203f�\212\307\322 \311#\210g\316=\206`�` =)\203f�\315\207\303\323!\203y�\212\305 \210\303\324!)\204y�\315\207\303\325!\203\230�\212\305 \210\303\324!)\204\230�\212\326 !\210h\327U)\204\230�\315\207\303\330!\205\262�\212\305 \210\303\324!)?\205\262�\331\332\n\"\205\262�\315\207" [foundp lim vhdl-syntactic-context looking-at "i" backward-sexp nil re-search-backward ";\\|\\b\\(architecture\\|case\\|configuration\\|entity\\|package\\|procedure\\|return\\|is\\|begin\\|process\\|procedural\\|block\\)\\b[^_]" move 95 vhdl-in-literal -1 t 59 "is\\|begin\\|process\\|procedural\\|block" "be\\|t" "e" ";\\|\\bwhen\\b[^_]" "bl\\|[glpur]" "end\\s-+\\w" "c" vhdl-backward-syntactic-ws 58 "f" assoc configuration] 5 (#$ . 126362)]) (defalias 'vhdl-corresponding-mid #[(&optional lim) "\300\301!\203�\302\207\300\303!\203�\304\207\305\207" [looking-at "is\\|block\\|generate\\|process\\|procedural" "begin" "then" "<else>" "end"] 2]) #@449 If the word at the current position corresponds to a "begin" keyword, then return a vector containing enough information to find the corresponding "end" keyword, else return nil. The keyword to search forward for is aref 0. The column in which the keyword must appear is aref 1 or nil if any column is suitable. Assumes that the caller will make sure that we are not in the middle of an identifier that just happens to contain a "begin" keyword. (defalias 'vhdl-corresponding-end #[(&optional lim) "\212\302!\205\263�h\303U?\205\263�\304 !?\205\263�\305 !\205\263�\302\306!\203@�\307\310\311`!\205<�\312`!\206<�\212\313 !\210\314 !\210\312`!)\"\202\263�\302\315!\203e�\307\310\311`!\205a�\312`!\206a�\212\313 !\210\314 !\210\312`!)\"\202\263�\302\316!\203r�\307\310\317\"\202\263�\302\320!\203\221�\307\310\312`!\206\215�\212\313 !\210\314 !\210\312`!)\"\202\263�\302\321!\205\263�\307\322\311`!\205\262�\312`!\206\262�\212\313 !\210\314 !\210\312`!)\")\207" [vhdl-begin-fwd-re lim looking-at 95 vhdl-in-literal vhdl-begin-p "[igl]" vector "end" vhdl-last-word vhdl-first-word vhdl-beginning-of-statement-1 vhdl-backward-skip-label "be\\|[ef]" "[cur]" nil "bl\\|p" "t" "elsif\\|else\\|end\\s-+if"] 4 (#$ . 127790)]) (byte-code "\301B\303\302B\304\301\207" [current-load-list vhdl-end-fwd-re vhdl-end-bwd-re "\\b\\(end\\|else\\|elsif\\)\\b\\([^_]\\|\\'\\)" "\\b\\(end\\|else\\|elsif\\)\\b[^_]"] 2) #@260 Return t if we are looking at a real "end" keyword. Assumes that the caller will make sure that we are looking at vhdl-end-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain an "end" keyword. (defalias 'vhdl-end-p #[(&optional lim) "\301\302!?\206�\212\303\304\305#\210g\306=\206�`=)\207" [lim looking-at "else" re-search-backward ";\\|\\bwhen\\b[^_]" move 59] 4 (#$ . 129203)]) #@626 If the word at the current position corresponds to an "end" keyword, then return a vector containing enough information to find the corresponding "begin" keyword, else return nil. The keyword to search backward for is aref 0. The column in which the keyword must appear is aref 1 or nil if any column is suitable. The supplementary keyword to search forward for is aref 2 or nil if this is not required. If aref 3 is t, then the "begin" keyword may be found in the middle of a statement. Assumes that the caller will make sure that we are not in the middle of an identifier that just happens to contain an "end" keyword. (defalias 'vhdl-corresponding-begin #[(&optional lim) "\212\303\304 !\205\310�\305\n!?\205\310�\306\n!\205\310�\304\307!\203'�\310\311\312`!\313\303$\202\310�`\314 \210\315\303w\210\304\316!\203A�\310\317\312!\320\303$\202\310�\304\321!\203V�\310\322\224\322\225{\312!\303\211$\202\310�\304\323!\203k�\310\322\224\322\225{\312!\303\324$\202\310�\304\325!\203|�\310\326\312!\303\211$\202\310�\304\327!\203\215�\310\330\312!\331\303$\202\310�\304\332!\203\236�\310\333\312!\334\303$\202\310�\304\335!\203\257�\310\336\312!\337\303$\202\310�\304\340!\203\300�\310\341\312!\303\211$\202\310�\310\342\312!\343\303$*\207" [pos vhdl-end-fwd-re lim nil looking-at vhdl-in-literal vhdl-end-p "el" vector "if\\|elsif" vhdl-first-word "then" forward-sexp " \n" "if\\b[^_]" "else\\|elsif\\|if" "else\\|then" "component\\b[^_]" 1 "\\(units\\|record\\)\\b[^_]" t "\\(block\\|process\\|procedural\\)\\b[^_]" "begin" "case\\b[^_]" "case" "is" "generate\\b[^_]" "generate\\|for\\|if" "generate" "loop\\b[^_]" "loop\\|while\\|for" "loop" "for\\b[^_]" "for" "begin\\|architecture\\|configuration\\|entity\\|package\\|procedure\\|function" (("begin") ("architecture" . "is") ("configuration" . "is") ("entity" . "is") ("package" . "is") ("procedure" . "is") ("function" . "is"))] 5 (#$ . 129660)]) (byte-code "\301B\302\301\207" [current-load-list vhdl-leader-re "\\b\\(block\\|component\\|process\\|procedural\\|for\\)\\b[^_]"] 2) (defalias 'vhdl-end-of-leader #[nil "\212\300\301!\203$�\212\302 \210\303\304w\210g\305U)\203�\302\306!\210\202 �\302 \210`\202U�\300\307!\2032�\302\306!\210`\202U�\300\310!\203T�\302\306!\210\303\304w\210\300\311!\203P�\302 \210\303\304w\210\202@�`\202U�\304)\207" [looking-at "block\\|process\\|procedural" forward-sexp " \n" nil 40 2 "component" "for" "[,:(]"] 2]) (byte-code "\301B\302\301\207" [current-load-list vhdl-trailer-re "\\b\\(is\\|then\\|generate\\|loop\\)\\b[^_]"] 2) #@89 A regular expression for searching forward that matches all known "statement" keywords. (defconst vhdl-statement-fwd-re "\\b\\(if\\|for\\|while\\)\\b\\([^_]\\|\\'\\)" (#$ . 132207)) #@90 A regular expression for searching backward that matches all known "statement" keywords. (defconst vhdl-statement-bwd-re "\\b\\(if\\|for\\|while\\)\\b[^_]" (#$ . 132395)) #@277 Return t if we are looking at a real "statement" keyword. Assumes that the caller will make sure that we are looking at vhdl-statement-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "statement" keyword. (defalias 'vhdl-statement-p #[(&optional lim) "\300\301!\203#�\212\302\303!\210\304\305w\210\300\306!)\203#�\212\307 \210\300\310!)\204#�\311\207\300\312!\2036�\212\307 \210\300\310!)\2046�\311\207\300\313!\205=�\311\207" [looking-at "f" forward-sexp 2 " \n" nil "in\\b[^_]" backward-sexp "end\\s-+\\w" t "i" "w"] 2 (#$ . 132573)]) #@53 Regexp describing a case statement alternative key. (defconst vhdl-case-alternative-re "when[( \n][^;=>]+=>" (#$ . 133188)) #@272 Return t if we are looking at a real case alternative. Assumes that the caller will make sure that we are looking at vhdl-case-alternative-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "when" keyword. (defalias 'vhdl-case-alternative-p #[(&optional lim) "\212\302\204'�\303\304 \305#\203'�h\306U\204�\307 !\203!�\310u\210\202�\311\211\203�g\312=\2060�` =*\207" [foundp lim nil re-search-backward ";\\|<=" move 95 vhdl-in-literal -1 t 59] 5 (#$ . 133320)]) (byte-code "\303B \304\nQ\303\207" [current-load-list vhdl-begin-bwd-re vhdl-end-bwd-re vhdl-b-t-b-re "\\|"] 3) #@57 Move backward to the previous "begin" or "end" keyword. (defalias 'vhdl-backward-to-block #[(&optional lim) "\305\204P�\306 \n\307#\203P�h\310U\204�\311\n!\203 �\312u\210\202�\313 !\2038�h\310U\2048�\314\n!\2038�\315\211\202�\313\f!\203�h\310U\204�\316\n!\203�\317\211\203�)\207" [foundp vhdl-b-t-b-re lim vhdl-begin-fwd-re vhdl-end-fwd-re nil re-search-backward move 95 vhdl-in-literal -1 looking-at vhdl-begin-p begin vhdl-end-p end] 5 (#$ . 133973)]) #@88 Move forward across one balanced expression (sexp). With COUNT, do it that many times. (defalias 'vhdl-forward-sexp #[(&optional count lim) "\206�\306\307\310\211\212\311V\203\340�\312\310w\210\313\f!\2039�h\314U\2049�\315 !\2049�\316 !\2039�\313\317!\2049�\320\321!\210\322 !\211\203\326�\323\n\311H\324Q\n\306H`\310\210`b\210)\310\211\211 \204\310�\325 \310\307#\203\310�\306\225\211\203\310�\311\224b\203\310�\203\225�\326 U\204\225�`V\204\244�h\314U\204\244�\315 !\211\203\267�\327=\203\261�\310\210\202e�\310u\210\202e�\313\317!\204\301�b\210\307\211\203j�\204\321�\320\330!\210.\202\331�\331 \210S\211\202�`) b\210,\310\207" [count target end-vec case-fold-search vhdl-end-fwd-re lim 1 t nil 0 " \n" looking-at 95 vhdl-in-literal vhdl-end-p "else" error "Containing expression ends prematurely in vhdl-forward-sexp" vhdl-corresponding-end "\\b\\(" "\\)\\b\\([^_]\\|\\'\\)" re-search-forward current-indentation comment "Unbalanced keywords in vhdl-forward-sexp" forward-sexp here placeholder literal foundp eol column end-re] 7 (#$ . 134445) "p"]) #@133 Move backward across one balanced expression (sexp). With COUNT, do it that many times. LIM bounds any required backward searches. (defalias 'vhdl-backward-sexp #[(&optional count lim) "\206�\306\307\310\211\212\311V\203]\312\313!\203%�h\314U\204%�\315\f!\203D�\316 \210\312 !\203D�h\314U\204D�\315\f!\204D�\317\f!\203D�\320\321!\210\322\f!\211\203Vh\314U\204V\323\n\311H\324Q\n\306H\n\325H`\310\211\211\211 !\"#$% \204K\326%\f\307#\203K\306\224\306\225{\211\203K$\203\245�\327 $U\204\245�#\203\261�i$U\203\261�h\314U\204\261�\315\f!\203\267�\330u\210\202s�\n\331H\211%\203D%<\203\333�\332%\"\211%\203D%A\211%\203D\323%\324Q\211%\203s�\212`! \2047\333%\"\307#\2037\306\224b\2037h\314U\204\315!!\211\2030\334=\203*`&\310\210`&b\210)\"^b\210\202\352�\310u\210\202\352�`\211 \203\357� )\203s� b\210\202s�\307\211 \203x� \204T\320\335!\210.S\211\202�`) b\210,\310\207" [count target begin-vec case-fold-search lim vhdl-begin-fwd-re 1 t nil 0 looking-at "else\\b\\([^_]\\|\\'\\)" 95 vhdl-in-literal backward-sexp vhdl-begin-p error "Containing expression ends prematurely in vhdl-backward-sexp" vhdl-corresponding-begin "\\b\\(" "\\)\\b[^_]" 3 re-search-backward current-indentation -1 2 assoc re-search-forward comment "Unbalanced keywords in vhdl-backward-sexp" keyword literal foundp last-forward last-backward internal-p column begin-re here] 9 (#$ . 135558) "p"]) #@83 Move backward out of one level of blocks. With argument, do this that many times. (defalias 'vhdl-backward-up-list #[(&optional count limit) "\206�\304\305\212\306V\203$�\307\n!\203�\310\311!\210\312 !\210S\211\202\n�`) b*\207" [count target vhdl-defun-re limit 1 nil 0 looking-at error "Unbalanced blocks" vhdl-backward-to-block] 3 (#$ . 137005) "p"]) #@42 Move forward to the end of a VHDL defun. (defalias 'vhdl-end-of-defun #[(&optional count) "\301\302 \210\303\304!\204�\305\306!\210\307 )\207" [case-fold-search t vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp] 2 (#$ . 137373) nil]) #@54 Put mark at end of this "defun", point at beginning. (defalias 'vhdl-mark-defun #[nil "\301\302 \210\303 \210\302 \210\304\305!\204�\306\307!\210\310 \210\311 )\207" [case-fold-search t push-mark vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp exchange-point-and-mark] 2 (#$ . 137680) nil]) #@485 Move backward to the beginning of a VHDL library unit. Returns the location of the corresponding begin keyword, unless search stops due to beginning or end of buffer. Note that if point is between the "libunit" keyword and the corresponding "begin" keyword, then that libunit will not be recognised, and the search will continue backwards. If point is at the "begin" keyword, then the defun will be recognised. The returned point is at the first character of the "libunit" keyword. (defalias 'vhdl-beginning-of-libunit #[nil "`\212\306v\210`T)\307\211\211\n\204\201�\310 \307\311#\203\201�h\312U\204-�\313e!\204-�\314 \2043�\315u\210\202�`\n\204{�\316\317 \320#\203{�\321\224\211\203{�h\312U\204V�\313\f!\211\203u� \322=\203o�`\307\210`b\210) ^b\210\2025�\307u\210\2025�\211\2039�\fb\210\202�\n-\207" [placeholder literal foundp last-backward last-forward vhdl-libunit-re 1 nil re-search-backward move 95 vhdl-in-literal vhdl-libunit-p -1 re-search-forward "\\bis\\b[^_]" t 0 comment here] 6 (#$ . 138045)]) #@199 Move backward to the beginning of a VHDL defun. With argument, do it that many times. Returns the location of the corresponding begin keyword, unless search stops due to beginning or end of buffer. (defalias 'vhdl-beginning-of-defun #[(&optional count) "\206�\306\307`\310\211\311V\203\243�\310\nb\210\212\306v\210`T)\310\211 \204\233�\312\310\313#\203\233�h\314U\204=�\315e!\203C�\316u\210\202$�\317 \211\203$�` \204\225�\320 \307#\203\225�h\314U\204n�\321 \322\216\315\n!\211*\203\216�\f\323=\203\210�`\310\210`b\210)^b\210\202L�\310u\210\202L�\311\224\211\203P�\nb\210\202$�+S\211\202 �\324 \210 ,\207" [count foundp last-forward case-fold-search literal begin-string 1 t nil 0 re-search-backward move 95 vhdl-in-literal -1 vhdl-corresponding-defun search-forward match-data ((set-match-data save-match-data-internal)) comment vhdl-keep-region-active last-backward vhdl-defun-re save-match-data-internal here] 5 (#$ . 139079) "p"]) #@457 Go to the beginning of the innermost VHDL statement. With prefix arg, go back N - 1 statements. If already at the beginning of a statement then go to the beginning of the preceding one. If within a string or comment, or next to a comment (only whitespace between), move by sentences instead of statements. When called from a program, this function takes 2 optional args: the prefix arg, and a buffer position limit which is the farthest back to search. (defalias 'vhdl-beginning-of-statement #[(&optional count lim) "\206�\306\307 \206 �e`\310\212 b\210\311` \310\211$)t\203>�\312\n8\2046�\313\n8\2046�\314\315 P!\203>�\316[!\210\202O�\317V\203O�\320 !\210S\211\202?�` ]b\210-\321 \207" [count lim state here case-fold-search comment-start-skip 1 t nil parse-partial-sexp 3 4 looking-at "[ ]*" forward-sentence 0 vhdl-beginning-of-statement-1 vhdl-keep-region-active] 6 (#$ . 140051) "p"]) (byte-code "\303B\304 \305\nR\303\207" [current-load-list vhdl-begin-fwd-re vhdl-statement-fwd-re vhdl-e-o-s-re ";\\|" "\\|"] 4) #@29 Very simple implementation. (defalias 'vhdl-end-of-statement #[nil "\301!\207" [vhdl-e-o-s-re re-search-forward] 2 (#$ . 141095) nil]) (byte-code "\303B\304 \305\nR\303\207" [current-load-list vhdl-begin-bwd-re vhdl-statement-bwd-re vhdl-b-o-s-re ";\\|(\\|)\\|\\bwhen\\b[^_]\\|" "\\|"] 4) #@107 Move to the start of the current statement, or the previous statement if already at the beginning of one. (defalias 'vhdl-beginning-of-statement-1 #[(&optional lim) "\206�e``\306\306\307\310\217\204 �\311\312!\210\306u\210\313 !\210\314 ?\205o?\205\315\f\316#\205h\317U\204>�\320!\203D�\321u\210\202 �g\322=\203W�\306u\210\313 !\210\314\211\202!�g\323=\203x�\306u\210`\324 \210`W\203 �\nb\210\313 !\210\314\211\202!�g\325=\203\213�\306u\210\313 !\210\314\211\202!�\326 !\203\315�h\317U\204\315�\327\306!\203\315�\326!\203\273�\212`\330 b\210\313 !\210` W\203\267�`)\202\304�\312v\210\313 !\210`\nb\210\314\211\202!�\326!\203\346�h\317U\204\346�\331\306!\203\346�\314\211\202!�\326!\203\332!\203\212`\326!\210\333\225b\210\313 !\210` W\203 `)\nb\210\314\211\202!�\321u\210\202 �,\207" [lim donep pos here vhdl-b-o-s-re vhdl-begin-fwd-re nil (byte-code "\300 \210\301\207" [backward-sexp t] 1) ((error)) backward-up-list 1 vhdl-forward-syntactic-ws t re-search-backward move 95 vhdl-in-literal -1 40 41 backward-sexp 59 looking-at vhdl-begin-p vhdl-end-of-leader vhdl-statement-p vhdl-case-alternative-p 0 vhdl-leader-re vhdl-statement-fwd-re vhdl-case-alternative-re] 5 (#$ . 141395)]) #@124 If there is an enclosing library unit at bod, with it's "begin" keyword at placeholder, then return the library unit type. (defalias 'vhdl-get-library-unit #[(bod placeholder) "`\303 \210`b\210)\212 b\210\304\305\306\217\210`X)\205[�\212\nb\210\307\310!\203)�\311\202Z�\307\312!\2033�\313\202Z�\307\314!\203=�\315\202Z�\307\316!\205Z�\212\nb\210\317 \210\320!\210\307\321!\203X�\322\202Y�\323)))\207" [here placeholder bod beginning-of-line nil (vhdl-forward-sexp 1 bod) ((error)) looking-at "e" entity "a" architecture "c" configuration "p" forward-sexp vhdl-forward-syntactic-ws "body\\b[^_]" package-body package] 3 (#$ . 142629)]) #@130 Finds and records all the closest opens. lim is the furthest back we need to search (it should be the previous libunit keyword). (defalias 'vhdl-get-block-state #[(&optional lim) "`\206�e\306\211\211\211\211\211\211\211\211\212\214`}\210\306\307\310\217)\211\2031� `V\203\234�\f\204\234�\311!\211\312=\203u�`\313!\306\314\315\217\211\203j�X\203j� \2041�\2021�\316\2021�\317=\2031�\320 \210`\306\306\321\322\217\206\220�\323 \210` \2041�\2021�) \203\263�\f\203\253�\f W\203\263� \306\306\306\324\f \n$. \207" [lim containing-paren containing-mid containing-begin containing-sexp preceding-sexp nil (byte-code "\300`\301\302#\207" [scan-lists -1 1] 4) ((error)) vhdl-backward-to-block begin vhdl-corresponding-mid (byte-code "\212\301\302\"\210`)\207" [lim vhdl-forward-sexp 1] 3) ((error)) t end forward-sexp (byte-code "\301\302\"\210`\207" [lim vhdl-backward-sexp 1] 3) ((error)) backward-sexp vector sexp-end sexp-mid sexp-start keyword here] 12 (#$ . 143276)]) (byte-code "\303B \304\nQ\303\207" [current-load-list vhdl-case-alternative-re vhdl-case-header-key vhdl-s-c-a-re "\\|"] 3) #@144 Skip forward over case/when bodies, with optional maximal limit. If no next case alternative is found, nil is returned and point is not moved. (defalias 'vhdl-skip-case-alternative #[(&optional lim) "\206�d`\306\211`W\203R�\n\204R�\307\f\310#\203\f�\311 \312\216\313 *\204\f�\314\224 U\204\f�\314\224b\210\315\316!\203K�\307\317\320#\203K�\321 \210\322 \210\202\f�\320\320\202\f� \204Y� b\210 ,\207" [lim foundp donep here vhdl-s-c-a-re save-match-data-internal nil re-search-forward move match-data ((set-match-data save-match-data-internal)) vhdl-in-literal 0 looking-at "case" "\\bis[^_]" t backward-sexp vhdl-forward-sexp] 4 (#$ . 144438)]) #@121 Skip backward over a label, with optional maximal limit. If label is not found, nil is returned and point is not moved. (defalias 'vhdl-backward-skip-label #[(&optional lim) "\206�e\303\212\304!\210h\305=\205�\306 \210`\307\n!)\205!� b*\207" [lim placeholder vhdl-label-key nil vhdl-backward-syntactic-ws 58 backward-sexp looking-at] 2 (#$ . 145102)]) #@121 Skip forward over a label, with optional maximal limit. If label is not found, nil is returned and point is not moved. (defalias 'vhdl-forward-skip-label #[(&optional lim) "\206�d\302 !\205�\303\225b\210\304!)\207" [lim vhdl-label-key looking-at 0 vhdl-forward-syntactic-ws] 2 (#$ . 145468)]) #@67 Guess the syntactic description of the current line of VHDL code. (defalias 'vhdl-get-syntactic-context #[nil "\212\214\306 \210`\307\310\310\310\310\3103\3104\3105\3106\3107\3108\3109\310:\310;\310<\310=\212\311 :`;):\203V�\312;:\"\211<\203V�<;B=B=\313;!\211\203q�\n\314H\n\315H\n\316H3\n\317H4\f\203\223�\212\fb\210\320>!\203\204�\321 5`?\306 \210`?b\210*\202\224�e;b\210\322\310w\210\323;!g7 ?\205\263�\320@!\205\263�\324 8 ?\205\303�\320A!\205\303�\325 9\326;!\210h6b\210\322\310w\210 \327>\203\360� `?\330y\210`?b\210)B=B=\202\374\f\204{\212 \204\331;!\210\202 b\210``?\332 \210`?b\210)U\204\331;!\210o\203\"\333!\210`:)8\2037\334:B=B=\202\3749\203H\335:B=B=\202\374\326;!\210o\204Wh\336U\203c\337:B=B=\202\374\331;!\210o\203p\333!\210\340`B=B=\202\3743\204\326\f!\2107\341=\203\244\fb\210\342`?\332 \210`?b\210)B=B=\202\3746\343=\203\304\fb\210\344`?\332 \210`?b\210)B=B=\202\374\212\fTb\210\322\310w\210\320\345!)\204\375\212\331\f!\210\346\310x\210`\fX)\203\375\fb\210\347`?\332 \210`?b\210)B=B=\202\374\331\f!\210\333!\210\350`?\332 \210`?b\210)B=B=\202\3748\203R\3204!\203R\fb\210\320B!\2038\351 \210\331\310!\210\352`?\332 \210`?b\210)!\210\334`B=B=\202\3749\203\202\fb\210\320B!\203h\351 \210\331\310!\210\352`?\332 \210`?b\210)!\210\335`B=B=\202\3746\336U\2048\203\235\320B!\204\212\352\f!)\204\320C!\203\251\353 \204\212\331\f!\210\333!\210`\211:)V\203:\fU\204\212:b\210\320D!?\206\324\314\225V)\203:E\212:b\210\354!\210`\211E)V\203\212Eb\210E\332 \210`)=\203E:)\340:B=B=8\203\374\334\310B=B=\202\374\320D!\203Q\355\f!\203Q\fb\210\320B!\203;\351 \210\331\310!\210\356`?\332 \210`?b\210)B=B=\202\3745\203]5b\210\202c\fb\210\351 \210\333!\210`:\310F\320D!\203\220`F\357!\204w\320D!\210\314\225b\210\333!\210`:\202mF\203\247`U\203\247\360FB=B=\202\373`W\203\306\337:B=B=8\203\373\334\310B=B=\202\373\fb\210\320B!\203\327\351 \210\331\310!\210\352`?\332 \210`?b\210)!\210\361`B=B=8\203\373\334\310B=B=)b\210\322\310w\210\320\345!\203\362\310B=B==.\207" [indent-point case-fold-search vec literal containing-sexp preceding-sexp beginning-of-line t nil vhdl-beginning-of-libunit vhdl-get-library-unit vhdl-get-block-state 0 1 2 3 looking-at vhdl-end-of-leader " " vhdl-in-literal vhdl-begin-p vhdl-end-p vhdl-backward-syntactic-ws (string comment) -1 vhdl-beginning-of-statement-1 back-to-indentation vhdl-forward-syntactic-ws block-open block-close 59 statement statement-cont 41 arglist-close 40 arglist-intro "--" " (" arglist-cont-nonempty arglist-cont forward-sexp vhdl-backward-skip-label vhdl-statement-p vhdl-forward-skip-label vhdl-case-alternative-p case-alternative vhdl-skip-case-alternative statement-case-intro statement-block-intro comment containing-begin containing-mid containing-leader char-before-ip char-after-ip begin-after-ip end-after-ip placeholder lim library-unit vhdl-syntactic-context vhdl-leader-re here vhdl-begin-fwd-re vhdl-end-fwd-re vhdl-trailer-re vhdl-statement-fwd-re vhdl-case-alternative-re new incase-p] 3 (#$ . 145773)]) #@118 Lineup the current arglist line with the arglist appearing just after the containing paren which starts the arglist. (defalias 'vhdl-lineup-arglist #[(langelem) "\212\212@\305>\203 �\306 \210\307\310!\210\311`\312\210` b\210)w\210\202$�Ab\210`)\212Ab\210i)\212\306 \210\313\314!)\203M�\315\225b\210\316 \210\312u\210\317 \210i Z\202x�\nb\210l\204u�`\312\210` b\210)\312u\210\311\312w\210`\317 \210`\fW\203t� b\210*i Z+\207" [langelem here containing-sexp cs-curcol eol (arglist-intro arglist-cont-nonempty) beginning-of-line backward-up-list 1 " " nil looking-at "[ ]*)" 0 backward-sexp vhdl-forward-syntactic-ws] 3 (#$ . 149007)]) #@60 Lineup an arglist-intro line to just after the open paren. (defalias 'vhdl-lineup-arglist-intro #[(langelem) "\212\212Ab\210i)\212\304 \210\305\306!\210\307`\310\210` b\210)w\210i)\n Z\311Z+\207" [langelem here ce-curcol cs-curcol beginning-of-line backward-up-list 1 " " nil -1] 4 (#$ . 149658)]) #@133 Support old behavior for comment indentation. We look at vhdl-comment-only-line-offset to decide how to indent comment only-lines. (defalias 'vhdl-lineup-comment #[(langelem) "\212\302 \210iY\203�\303 \202'�n\204� \242\206'� \202'� \243\206'� \242\206'�\304)\207" [comment-column vhdl-comment-only-line-offset back-to-indentation vhdl-comment-indent -1000] 2 (#$ . 149969)]) #@55 Line up statement-cont after the assignment operator. (defalias 'vhdl-lineup-statement-cont #[(langelem) "\212A\212`\306 \210`\nb\210)b\210\307\310`\311\210`\nb\210)\312#\205.�``\306 \210`\nb\210)Z) b\210i\311 \204\212�``\311\210`\nb\210)W\203\212�\307\313`\311\210`\nb\210)\314#\210\315A!\203f�\311u\210\2027�h\316U\203\201�`\311\210`\nb\210)\317`\320\211#^b\210\2027�\321\322!?\211\203;� \204\223�\202\245� \204\240�\311u\210\323\311w\210\324i Z\fZ-\207" [langelem relpos here assignp curcol foundp back-to-indentation re-search-forward "\\(<\\|:\\)=" nil t "\\(<\\|:\\)=\\|(" move vhdl-in-literal 40 scan-lists 1 looking-at "\\s-*$" " " 0 vhdl-basic-offset] 6 (#$ . 150354)]) #@60 Check if point is to right of beginning comment delimiter. (defalias 'vhdl-in-comment-p #[nil "`\212\301 \210\302\303\304#*\207" [position beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" t] 4 (#$ . 151060)]) (put 'vhdl-in-comment-p 'byte-optimizer 'byte-compile-inline-expand) #@32 Check if point is in a string. (defalias 'vhdl-in-string-p #[nil "`\212\301 \210\302\303\304#*=\207" [position beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*\"[^\"]*" t] 5 (#$ . 151368)]) (put 'vhdl-in-string-p 'byte-optimizer 'byte-compile-inline-expand) #@45 Check if point is in a comment or a string. (defalias 'vhdl-in-comment-or-string-p #[nil "`\212\301 \210\302\303\304#*\205�`\212\301 \210\302\305\304#*=\207" [position beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" t "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*\"[^\"]*"] 5 (#$ . 151654)]) (put 'vhdl-in-comment-or-string-p 'byte-optimizer 'byte-compile-inline-expand) #@224 If preceeding character is part of a word or a paren then hippie-expand, else if right of non whitespace on line then tab-to-tab-stop, else if last command was a tab or return then dedent one step, else indent `correctly'. (defalias 'vhdl-electric-tab #[(&optional prefix-arg) "\306\307\310\311 #\210hz\312U\203�\n?\306\313 !\210*\202c�h\314U\204(�h\315U\2035�\n?\306\316 !\210*\202c�i\317 V\203B�\320 \210\202c�\321=\204P�\322=\203`�\317 \323U\204`�\324\306\"\210\202c�\325 \210\321\211\204s�\307\310\326 #\210)\207" [result vhdl-mode-syntax-table vhdl-word-completion-case-sensitive case-replace case-fold-search prefix-arg nil modify-syntax-entry 95 "w" 119 vhdl-expand-abbrev 40 41 vhdl-expand-paren current-indentation tab-to-tab-stop vhdl-electric-tab vhdl-electric-return 0 backward-delete-char-untabify vhdl-indent-line "_" last-command vhdl-basic-offset this-command vhdl-underscore-is-part-of-word] 4 (#$ . 152047) "*P"]) #@97 newline-and-indent or indent-new-comment-line if in comment and preceding character is a space. (defalias 'vhdl-electric-return #[nil "h\301U\203�`\212\302 \210\303\304\305#*\203�\306 \207\307 \207" [position 32 beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" t indent-new-comment-line newline-and-indent] 4 (#$ . 153003) nil]) #@66 Array variable for progress information: 0 begin, 1 end, 2 time. (defvar vhdl-progress-info nil (#$ . 153364)) #@82 Indent the current line as VHDL code. Returns the amount of indentation change. (defalias 'vhdl-indent-line #[nil "\306 d`Z@@\307=\203�\310@!\nY\203�\310@!\202&�\311\312\313\310\"\"\211\314 Z \2036�\315\316 #\210\317\f!\204\\�`\320 \210`b\210)`\321 \210`b\210)|\210\320 \210 j\210``\321 \210`b\210)W\203s�\321 \210\202\200�d Z`V\203\200�d Zb\210\322\323!\210\203\315�\324\324H\325\fV\203\232�\326\202\233�\f\\I\210\327 A@\330HZW\203\315�\315\331`\326HZ\332_\324H\326HZ\245\333#\210\330\327 A@I\210\f,\207" [syntax pos comment-column indent shift-amt vhdl-echo-syntactic-information-p vhdl-get-syntactic-context comment vhdl-get-offset apply + mapcar current-indentation message "syntax: %s, indent= %d" zerop beginning-of-line back-to-indentation run-hooks vhdl-special-indent-hook 1 -500 0 current-time 2 "Indenting... (%2d%s)" 100 "%" here vhdl-progress-info vhdl-progress-interval] 7 (#$ . 153481) nil]) #@103 Indent whole buffer as VHDL code. Calls `indent-region' for whole buffer and adds progress reporting. (defalias 'vhdl-indent-buffer #[nil "\203\n�\302ed\303#\304ed\305#\210\203�\306\307!\210\305\211\207" [vhdl-progress-interval vhdl-progress-info vector 0 indent-region nil message "Indenting...done"] 4 (#$ . 154437) nil]) #@73 Indent region as VHDL code. Adds progress reporting to `indent-region'. (defalias 'vhdl-indent-region #[(start end column) "\203\n�\305 \n\306#\307 \n\f#\210\203�\310\311!\210\312\211\207" [vhdl-progress-interval start end vhdl-progress-info column vector 0 indent-region message "Indenting...done" nil] 4 (#$ . 154772) "r\nP"]) #@145 Indent each line of the list starting just after point. If optional arg ENDPOS is given, indent each line, stopping when ENDPOS is encountered. (defalias 'vhdl-indent-sexp #[(&optional endpos) "\212`\303\304\"\210`\305\n \304#+\207" [endpos end beg vhdl-forward-sexp nil indent-region] 4 (#$ . 155113) nil]) #@46 Show syntactic information for current line. (defalias 'vhdl-show-syntactic-information #[nil "\300\301\302 \"\210\303 \207" [message "syntactic analysis: %s" vhdl-get-syntactic-context vhdl-keep-region-active] 3 (#$ . 155430) nil]) #@47 Check syntactic information for current line. (defalias 'vhdl-regress-line #[(&optional arg) "\212\305\210\306\307`\310 \210`b\210)\311#\205�\312u\210\313p!)\314 \305\315\316\n\"\210\f\204C� \203C� <\203C� \232\204n�\317\320 #\210\202n�\212\310 \210\321\322!\204m�\305\210\306\307`\310 \210`b\210)\311#\203d�\323 \210\324c\210\325\326 \"c\210)+\327 \207" [here expurgated actual expected arg nil search-backward " -- ((" beginning-of-line t 4 read vhdl-get-syntactic-context mapcar #[(elt) "@\302>?\205�\303 C\"\211\207" [elt expurgated (entity configuration package package-body architecture) append] 3] error "Should be: %s, is: %s" looking-at "^\\s-*\\(--.*\\)?$" kill-line " -- " format "%s" vhdl-keep-region-active] 4 (#$ . 155669) "P"]) #@469 The format of this alist is (MODES [or MODE] REGEXP ALIGN-PATTERN SUBEXP). It is searched in order. If REGEXP is found anywhere in the first line of a region to be aligned, ALIGN-PATTERN will be used for that region. ALIGN-PATTERN must include the whitespace to be expanded or contracted. It may also provide regexps for the text surrounding the whitespace. SUBEXP specifies which sub-expression of ALIGN-PATTERN matches the white space to be expanded/contracted. (defvar vhdl-align-alist '((vhdl-mode "\\<\\(constant\\|quantity\\|signal\\|terminal\\|variable\\)[ ]" "\\<\\(constant\\|quantity\\|signal\\|terminal\\|variable\\)\\([ ]+\\)" 2) (vhdl-mode ":[^=]" "\\([ ]*\\):[^=]") (vhdl-mode ":[ ]*\\(in\\|out\\|inout\\|buffer\\|\\)\\>" ":[ ]*\\(in\\|out\\|inout\\|buffer\\|\\)\\([ ]+\\)" 2) (vhdl-mode "==" "\\([ ]*\\)==" 1) (vhdl-mode ":=" "\\([ ]*\\):=" 1) (vhdl-mode "<=" "\\([ ]*\\)<=" 1) (vhdl-mode "=>" "\\([ ]*\\)=>" 1) (vhdl-mode ":=" "\\([ ]*\\):=" 1) (vhdl-mode "<=" "\\([ ]*\\)<=" 1) (vhdl-mode "[ ]after\\>" "[^ ]\\([ ]+\\)after\\>" 1) (vhdl-mode "[ ]when\\>" "[^ ]\\([ ]+\\)when\\>" 1) (vhdl-mode "[ ]else\\>" "[^ ]\\([ ]+\\)else\\>" 1)) (#$ . 156435)) #@143 If REGEXP is not found on the first line of the region that clause is ignored. If this variable is non-nil, then the clause is tried anyway. (defvar vhdl-align-try-all-clauses t (#$ . 157633)) #@307 Attempt to align a range of lines based on the content of the lines. The definition of `alignment-list' determines the matching order and the manner in which the lines are aligned. If ALIGNMENT-LIST is not specified `vhdl-align-alist' is used. If INDENT is non-nil, indentation is done before aligning. (defalias 'vhdl-align-region #[(begin end &optional spacing alignment-list indent) "\206� \n\206 �\306\212\307\211 b\210\310 b\210\311 \210`\211 \203-�\312\f \307#\210+\313\314!\307\315\316\317#\210\205\236�\212b\210\307\212\307\210`)@\211@<\203i�@>\204r�@=\203\225�\204\203�\320A@\313#\203\225�\321 AA@AAA@\n%\210A+\202@�\204\254�\315\316\322#\210+\207" [alignment-list vhdl-align-alist spacing indent bol end 1 nil point-marker beginning-of-line indent-region t copy-alist modify-syntax-entry 95 "w" re-search-forward vhdl-align-region-1 "_" begin copy case-fold-search result vhdl-mode-syntax-table eol element major-mode vhdl-align-try-all-clauses vhdl-underscore-is-part-of-word] 7 (#$ . 157834) "r\np"]) #@400 Align a range of lines from BEGIN to END. The regular expression MATCH must match exactly one fields: the whitespace to be contracted/expanded. The alignment column will equal the rightmost column of the widest whitespace block. SPACING is the amount of extra spaces to add to the calculated maximum required. SPACING defaults to 1 so that at least one space is inserted after the token in MATCH. (defalias 'vhdl-align-region-1 #[(begin end match &optional substr spacing) "\206�\306 \206 �\306\212\307\310\211\307\211\211b\210\307\210`\311 \210`\211\fW\203r�\212\312 \313#\203_�`\212\311 \210\312\314\313#*\204_� \224\fZ\211V\203_�)\307y\210`\212\307\210`) T\202,�\211b\210\212\307\210`) \310V\205\324�\312 \313#\203\276�`\212\311 \210\312\314\313#*\204\276� \225 \224Z \224\fZ \224b\210\315\n!\210\316\317Z\\\"\210\311 \210\307y\210`\212\307\210`) S\211\202\200�.\207" [spacing substr width eol bol lines 1 nil 0 beginning-of-line re-search-forward t "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" delete-char insert-char 32 max distance begin end match position] 7 (#$ . 158923)]) #@34 Align inline comments in region. (defalias 'vhdl-align-inline-comment-region-1 #[(beg end &optional spacing) "\212\306\211\307\310\311\312\313\f#\210 b\210`W\203X�\314\315!\2048�\314\316!\2038�\n\317\225\317\224Z] \320\225\320\224Z]\202Q�\314\321!\203Q�\317\225\317\224ZY\203Q� \320\225\320\224Z]\322\320!\210\202� b\210\206a�\320\n\\`W\205\304�\314\315!\204\275�\314\323!\204\214�\314\324!\203\275�\317\225\317\224ZY\203\275�\317\225b\210\317\224\317\225|\210\325\326\"\210\nX\203\252�j\210\202\275�\n \\X\203\271�\nj\210\202\275�j\210\322\320!\210\202h�\204\320�\311\312\327\f#\210 -\207" [case-fold-search high-length high-start result vhdl-mode-syntax-table beg 0 t nil modify-syntax-entry 95 "w" looking-at "^\\s-*\\(begin\\|end\\)\\>" "^\\(.*[^ \n-]+\\)\\s-*\\(--\\s-*.*\\)$" 1 2 "^\\(\\s-*\\))\\(--\\s-*.*\\)$" beginning-of-line "^.*[^ \n-]+\\(\\s-*\\)--" "^\\(\\s-*\\)--" insert-char 32 "_" end comment-column spacing end-comment-column vhdl-underscore-is-part-of-word] 4 (#$ . 160066)]) #@35 Align region without indentation. (defalias 'vhdl-align-noindent-region #[(beg end &optional spacing no-message) "\212\306 b\210\307 \210`\nb\210\310 \311 \n\"\210 \204�\312\313!\210\314 \n\315#\210 b\210\f\2049�\316 \n #\210\317 \n\"\210\202o� \nW\203^�\320\321\n\315#\203^�\310 \316  #\210\317 \"\210T\211b\210\2029� \nW\203o�\316 \n #\210\317 \n\"\210* ?\205x�\312\322!\207" [pos beg end no-message vhdl-align-groups spacing nil beginning-of-line point-marker untabify message "Aligning..." vhdl-fixup-whitespace-region t vhdl-align-region vhdl-align-inline-comment-region-1 re-search-forward "^\\s-*$" "Aligning...done"] 5 (#$ . 161106) "r\nP"]) #@43 Align group of lines between empty lines. (defalias 'vhdl-align-group #[(&optional spacing) "\212`\304\211\305\306\304\307#\203�\310 \202�d\nb\210\311\306\304\307#\203%�`\202&�e\312 \"\210\313\314!\210\315 \307#\210\316  #\210\317 \"\210\313\320!,\207" [end beg start spacing nil re-search-forward "^\\s-*$" t point-marker re-search-backward untabify message "Aligning..." vhdl-fixup-whitespace-region vhdl-align-region vhdl-align-inline-comment-region-1 "Aligning...done"] 4 (#$ . 161771) nil]) #@35 Align buffer without indentation. (defalias 'vhdl-align-noindent-buffer #[nil "\300ed\"\207" [vhdl-align-noindent-region] 3 (#$ . 162284) nil]) #@148 Align inline comments within a region. Groups of code lines separated by empty lines are aligned individually, if `vhdl-align-groups' is non-nil. (defalias 'vhdl-align-inline-comment-region #[(beg end &optional spacing no-message) "\212\306 b\210\307 \210`\nb\210\310 \311 \n\"\210 \204�\312\313!\210 b\210\f\204.�\314 \n #\210\202Z� \nW\203N�\315\316\n\317#\203N�\310 \314  #\210T\211b\210\202.� \nW\203Z�\314 \n #\210) ?\205c�\312\320!)\207" [pos beg end no-message vhdl-align-groups spacing nil beginning-of-line point-marker untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 re-search-forward "^\\s-*$" t "Aligning inline comments...done"] 5 (#$ . 162435) "r\nP"]) #@68 Align inline comments within a group of lines between empty lines. (defalias 'vhdl-align-inline-comment-group #[(&optional spacing) "\212`\303\211\304\305\303\306#\203�\307 \202�d\nb\210\310\305\303\306#\203%�`\202&�e\311 \"\210\312\313!\210\314 \"\210\312\315!,\207" [end beg start nil re-search-forward "^\\s-*$" t point-marker re-search-backward untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 "Aligning inline comments...done"] 4 (#$ . 163151) nil]) #@146 Align inline comments within buffer. Groups of code lines separated by empty lines are aligned individually, if `vhdl-align-groups' is non-nil. (defalias 'vhdl-align-inline-comment-buffer #[nil "\300ed\"\207" [vhdl-align-inline-comment-region] 3 (#$ . 163655) nil]) #@184 Fixup whitespace in region. Surround operator symbols by one space, eliminate multiple spaces (except at beginning of line), eliminate spaces at end of line, do nothing in comments. (defalias 'vhdl-fixup-whitespace-region #[(beg end &optional no-message) "\204�\303\304!\210\212 b\210\305 \nb\210\306\307 \310#\2032�\311\312!\313\232\203+�\306\314 \310#\210\202�\315\316!\210\202�\nb\210\306\317 \310#\203Y�\311\320!\313\232\203N�\306\314 \310#\210\2025�\315\321\322\211\211\320%\210\2025�\nb\210\323\324!\203j�\306\324 \310#\204\\�\323\325!\203\201�\306\325 \310#\203\201�\315\326\322\211#\210\202\\�\323\327!\203\230�\306\327 \310#\203\230�\315\330\322\211#\210\202\\�\323\331!\203\246�\306\331 \310#\204\\�\323\332!\203\275�\306\333 \310#\203\275�\315\334\322\211#\210\202\\�\323\333!\203\324�\306\333 \310#\203\324�\315\335\322\211#\210\202\\�\306\336 \310#\204\\�)?\205\345�\303\337!\207" [no-message end beg message "Fixing up whitespace..." point-marker re-search-forward "\\([^/:<>=]\\|^\\)\\(--\\|:\\|=\\|<\\|>\\|:=\\|<=\\|>=\\|=>\\)\\([^=>]\\|$\\)" t match-string 2 "--" ".*\n" replace-match "\\1 \\2 \\3" "\\(--\\|\\s-*\\([,;]\\)\\)" 1 "\\2 " nil looking-at "--.*\n" "\\s-+$" "" "\\s-+;" ";" "^\\s-+" "\\s-+--" "\\s-+" " " " " "\\S-+" "Fixing up whitespace...done"] 6 (#$ . 163929) "r"]) #@184 Fixup whitespace in buffer. Surround operator symbols by one space, eliminate multiple spaces (except at beginning of line), eliminate spaces at end of line, do nothing in comments. (defalias 'vhdl-fixup-whitespace-buffer #[nil "\300ed\"\207" [vhdl-fixup-whitespace-region] 3 (#$ . 165243) nil]) #@243 Beautify region by applying indentation, whitespace fixup, alignment, and case fixing to a resion. Calls functions `vhdl-indent-buffer', `vhdl-align-noindent-buffer' (variable `vhdl-align-groups' set to non-nil), and `vhdl-fix-case-buffer'. (defalias 'vhdl-beautify-region #[(beg end) "\303 \304#\210\305\306 \"\210)\307 \"\207" [beg end vhdl-align-groups vhdl-indent-region nil t vhdl-align-noindent-region vhdl-fix-case-region] 4 (#$ . 165547) "r"]) #@158 Beautify buffer by applying indentation, whitespace fixup, alignment, and case fixing to entire buffer. Calls `vhdl-beautify-region' for the entire buffer. (defalias 'vhdl-beautify-buffer #[nil "\300ed\"\207" [vhdl-beautify-region] 3 (#$ . 166011) nil]) #@51 Syntax of prompt inserted by template generators. (defconst vhdl-template-prompt-syntax "[^ =<>][^<>@.\n]*[^ =<>]" (#$ . 166272)) #@118 Indicates whether a template has been invoked by a hook or by key or menu. Used for undoing after template abortion. (defvar vhdl-template-invoked-by-hook nil (#$ . 166409)) (byte-code "\301\302\303\304\"\203 �\305\202�\306\"\207" [emacs-version defalias vhdl-character-to-event string-match "XEmacs" character-to-event identity] 5) #@49 Update the modeline string for VHDL major mode. (defalias 'vhdl-mode-line-update #[nil "\303\204 � \205\n�\304\205�\305 \205�\306R\307 \207" [vhdl-electric-mode vhdl-stutter-mode mode-name "VHDL" "/" "e" "s" force-mode-line-update] 4 (#$ . 166750)]) #@106 Toggle VHDL electric mode. Turn on if ARG positive, turn off if ARG negative, toggle if ARG zero or nil. (defalias 'vhdl-electric-mode #[(arg) "\203\n�\302!\203� ?\202�\303V\203�\304\202�\305\306 \207" [arg vhdl-electric-mode zerop 0 t nil vhdl-mode-line-update] 2 (#$ . 167012) "P"]) #@108 Toggle VHDL stuttering mode. Turn on if ARG positive, turn off if ARG negative, toggle if ARG zero or nil. (defalias 'vhdl-stutter-mode #[(arg) "\203\n�\302!\203� ?\202�\303V\203�\304\202�\305\306 \207" [arg vhdl-stutter-mode zerop 0 t nil vhdl-mode-line-update] 2 (#$ . 167312) "P"]) #@81 -- starts a comment, --- draws a horizontal line, ---- starts a display comment (defalias 'vhdl-electric-dash #[(count) "\203^� \203� `U\203�\306\nb\210\307\306!\210\310 \207h\311U\204$�\312 !\207\312 !\210\313\314!\210\315 \211\311U\203U�\316 \210\313\317!\210\315 \211\311U\203K�\310\320!\202Q�\321\f!C\211)\202\\�\321\f!C\322 )\207\312 !\207" [vhdl-stutter-mode abbrev-start-location last-abbrev-location count next-input unread-command-events nil beginning-of-line vhdl-comment-display 45 self-insert-command message "Enter '-' for horiz. line, 'CR' for commenting-out code, else enter comment" read-char vhdl-comment-display-line "Enter '-' for display comment, else continue coding" t vhdl-character-to-event vhdl-comment-insert] 3 (#$ . 167611) "p"]) #@27 '[' --> '(', '([' --> '[' (defalias 'vhdl-electric-open-bracket #[(count) "\203� \302U\203�h\303U\203�\304\305!\210\306\307\302\"\207\306\303\302\"\207\310 !\207" [vhdl-stutter-mode count 1 40 delete-char -1 insert-char 91 self-insert-command] 3 (#$ . 168383) "p"]) #@27 ']' --> ')', ')]' --> ']' (defalias 'vhdl-electric-close-bracket #[(count) "\203$� \302U\203$�h\303U\203�\304\305!\210\306\307\302\"\210\202!�\306\303\302\"\210\310 \207\311 !\207" [vhdl-stutter-mode count 1 41 delete-char -1 insert-char 93 blink-matching-open self-insert-command] 3 (#$ . 168659) "p"]) #@10 '' --> " (defalias 'vhdl-electric-quote #[(count) "\203� \303U\203�h\nU\203�\304\303!\210\305\306\303\"\207\305\307\303\"\207\310 !\207" [vhdl-stutter-mode count last-input-char 1 delete-backward-char insert-char 34 39 self-insert-command] 3 (#$ . 168971) "p"]) #@34 ';;' --> ' : ', ': ;' --> ' := ' (defalias 'vhdl-electric-semicolon #[(count) "\203<� \305U\203<�h\nU\203$�\306\307!\210h\310=\204�\311c\210\312c\210\313\211\207\f\313=\2037�h\310U\2037�\306\307!\210\314c\207\315\316\305\"\207\317 !\207" [vhdl-stutter-mode count last-input-char this-command last-command 1 delete-char -1 32 " " ": " vhdl-electric-colon "= " insert-char 59 self-insert-command] 3 (#$ . 169243) "p"]) #@17 ',,' --> ' <= ' (defalias 'vhdl-electric-comma #[(count) "\203%� \303U\203%�h\nU\203 �\304\305!\210h\306=\204�\307c\210\310c\207\311\312\303\"\207\313 !\207" [vhdl-stutter-mode count last-input-char 1 delete-char -1 32 " " "<= " insert-char 44 self-insert-command] 3 (#$ . 169669) "p"]) #@17 '..' --> ' => ' (defalias 'vhdl-electric-period #[(count) "\203%� \303U\203%�h\nU\203 �\304\305!\210h\306=\204�\307c\210\310c\207\311\312\303\"\207\313 !\207" [vhdl-stutter-mode count last-input-char 1 delete-char -1 32 " " "=> " insert-char 46 self-insert-command] 3 (#$ . 169964) "p"]) #@17 '==' --> ' == ' (defalias 'vhdl-electric-equal #[(count) "\203%� \303U\203%�h\nU\203 �\304\305!\210h\306=\204�\307c\210\310c\207\311\312\303\"\207\313 !\207" [vhdl-stutter-mode count last-input-char 1 delete-char -1 32 " " "== " insert-char 61 self-insert-command] 3 (#$ . 170260) "p"]) #@65 Insert a pair of round parentheses, placing point between them. (defalias 'vhdl-template-paired-parens #[nil "\300c\210\301u\207" ["()" -1] 1 (#$ . 170555) nil]) #@27 Insert alias declaration. (defalias 'vhdl-template-alias #[nil "`\304\305!\210\306\307\310\311`%\205B�\312c\210\306\313\314\314\n@=\206&� \n\211A@)>)\205+�\315\316Q\310\311#\2047�\317\320!\210\304\321!\210\306\307\322\"\210\323 )\207" [start standard vhdl-standard x vhdl-insert-keyword "ALIAS " vhdl-template-field "name" nil t " : " "[type" ams " or nature" "]" backward-delete-char 3 " IS " ";" vhdl-comment-insert-inline] 6 (#$ . 170723) nil]) #@22 Insert architecture. (defalias 'vhdl-template-architecture #[nil "\306 `\307\211\211\310\311\312!\210\313\314\307\310\f`%\211\205\205�\311\315!\210\212\307\316\317\320#\210\321\322\307\310#\323\324!\211\204E�\316\317\325#\210\210*\n\203Y� \326\232\204Y� c\210\202]�\313\327!\210\311\330!\210\331\332 \332!@=\206x� !\211\"A@)>)?\205~�\333 #\334>$.\207" [case-fold-search string entity-exists arch-name start margin current-indentation nil t vhdl-insert-keyword "ARCHITECTURE " vhdl-template-field "name" " OF " modify-syntax-entry 95 "w" re-search-backward "\\<entity \\(\\w+\\) is\\>" match-string 1 "_" "" "entity name" " IS" vhdl-template-begin-end 87 "ARCHITECTURE" (unit all) result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word standard vhdl-standard x vhdl-insert-empty-lines] 6 (#$ . 171181) nil]) #@31 Insert array type definition. (defalias 'vhdl-template-array #[(kind &optional secondary) "`\303\304!\210\305\306\307 ?`%\204� \205*�\303\310!\210\305\n\311=\203$�\312\202%�\313!\210\303\314!)\207" [start secondary kind vhdl-insert-keyword "ARRAY (" vhdl-template-field "range" nil ") OF " type "type" "nature" ";"] 6 (#$ . 172030) nil]) #@32 Insert an assertion statement. (defalias 'vhdl-template-assert #[nil "`\302\303!\210 \203 �\304c\210\305\306\307\310`%\205H� \203�\311c\210`\302\312!\210\305\313\307\211\211\211\310&\2044�`|\210`\302\314!\210\305\315\307\310#\204F�`|\210\316c)\207" [start vhdl-conditions-in-parenthesis vhdl-insert-keyword "ASSERT " "(" vhdl-template-field "condition (negated)" nil t ")" " REPORT " "string expression" " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 7 (#$ . 172377) nil]) #@51 Insert an attribute declaration or specification. (defalias 'vhdl-template-attribute #[nil "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query "attribute" "(d)eclaration or (s)pecification?" t 115 vhdl-template-attribute-spec vhdl-template-attribute-decl] 4 (#$ . 172872) nil]) #@34 Insert an attribute declaration. (defalias 'vhdl-template-attribute-decl #[nil "`\301\302!\210\303\304\305\306`%\205�\303\307\310\"\210\311 )\207" [start vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" " : " t "type" ";" vhdl-comment-insert-inline] 6 (#$ . 173174) nil]) #@36 Insert an attribute specification. (defalias 'vhdl-template-attribute-spec #[nil "`\301\302!\210\303\304\305\306`%\205%�\301\307!\210\303\310\311\"\210\303\312!\210\301\313!\210\303\314\315\")\207" [start vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" nil t " OF " "entity names | OTHERS | ALL" " : " "entity class" " IS " "expression" ";"] 6 (#$ . 173466) nil]) #@17 Insert a block. (defalias 'vhdl-template-block #[nil "\306 `\307\310\311!\210 b\210\312\313\307\314 `\315\\%\211\205X�\316v\210\316u\210\317c\210\312\320\307\314#\2033�\321c\210\2027�\322\323!\210\324\324\f@=\206H� \f\211A@)>)\204P�\310\325!\210\326\327\n#\210\330 +\207" [label start margin standard vhdl-standard x current-indentation nil vhdl-insert-keyword ": BLOCK " vhdl-template-field "label" t 8 1 "(" "[guard expression]" ")" delete-char -2 87 " IS" vhdl-template-begin-end "BLOCK" vhdl-comment-block] 7 (#$ . 173850) nil]) #@41 Insert a block configuration statement. (defalias 'vhdl-template-block-configuration #[nil "\303 `\304\305!\210\306\307\310\311`%\205%�\304\312!\210 j\210\304\313!\210\314\210 \n\\j*\207" [start margin vhdl-basic-offset current-indentation vhdl-insert-keyword "FOR " vhdl-template-field "block name" nil t "\n\n" "END FOR;" 0] 6 (#$ . 174396) nil]) #@27 Insert a break statement. (defalias 'vhdl-template-break #[nil "\302\303\304!\210`\305c\210\303\306!\210\307\310\311\312#\203�\307\313\314\"\210\202+�\315\316!\210\307\310\314\312#\2037�\307\317!\210`\320c\210\202 �`|\210\321 \204U�\303\322!\210\307\323\302\312#\203Q�`\202U�`|\210\303\324!\210 \203`�\325c\210\307\326\302\312#\203r� \203v�\327c\210\202v�`|\210\330c)\207" [position vhdl-conditions-in-parenthesis nil vhdl-insert-keyword "BREAK" " " "FOR " vhdl-template-field "[quantity name]" " USE " t "quantity name" " => " kill-word -1 "expression" ", " vhdl-sequential-statement-p " ON " "[sensitivity list]" " WHEN " "(" "[condition]" ")" ";"] 4 (#$ . 174755) nil]) #@26 Insert a case statement. (defalias 'vhdl-template-case #[(&optional kind) "\306 `\307 \204�\310 \203�\311\202�\312\f\313=\2034�\314\314!@=\2060� !\211\"A@)>)\203;�\315\316!\210\202V�\315\317!\210 b\210\320\321\307\322#\211\204P�\323\324!\210\325v\210\325u\210\320\326\307\322 `%\205\245�\315\327 \311=\203l�\330\202m�\331\332Q!\210\nj\210\315\333!\210\203\201�\327\261\210\334c\210\335y\210\n#\\j\210\315\336!\210`$\337c\210\n#\\j\210\315\340!\210$b)+\207" [label start margin kind vhdl-optional-labels standard current-indentation nil vhdl-sequential-statement-p is use all 87 vhdl-insert-keyword "CASE " ": CASE " vhdl-template-field "[label]" t delete-char 2 1 "expression" " " "IS" "USE" "\n\n" "END CASE" ";" -1 "WHEN " " => ;\n" "WHEN OTHERS => null;" vhdl-standard x vhdl-basic-offset position] 7 (#$ . 175442) nil]) #@37 Insert a sequential case statement. (defalias 'vhdl-template-case-is #[nil "\300\301!\207" [vhdl-template-case is] 2 (#$ . 176291) nil]) #@39 Insert a simultaneous case statement. (defalias 'vhdl-template-case-use #[nil "\300\301!\207" [vhdl-template-case use] 2 (#$ . 176434) nil]) #@33 Insert a component declaration. (defalias 'vhdl-template-component #[nil "\300 \207" [vhdl-template-component-decl] 1 (#$ . 176581) nil]) #@111 Insert a component configuration (uses `vhdl-template-configuration-spec' since these are almost equivalent). (defalias 'vhdl-template-component-conf #[nil "\302 \303\304!\205�\305c\210 j\210\306\307!\210\310=\205�\311*\207" [result margin current-indentation vhdl-template-configuration-spec t "\n" vhdl-insert-keyword "END FOR;" no-use 0] 3 (#$ . 176726) nil]) #@33 Insert a component declaration. (defalias 'vhdl-template-component-decl #[nil "\306 `\307\211\310\311!\210\312\313\307\314\n`%\211\205d�\315c\210 j\210\310\316!\210\317\317 @=\2065�\f \211A@)>)\204>�\320 \261\210\321c\210i\322\210 \\j\210\323\314\211\"\210\324c\210 \\j\210\325\314!\210\326\327!\210u,\207" [end-column name start margin standard vhdl-standard current-indentation nil vhdl-insert-keyword "COMPONENT " vhdl-template-field "name" t "\n\n" "END COMPONENT" 87 " " ";" 0 vhdl-template-generic-list "\n" vhdl-template-port-list beginning-of-line 2 x vhdl-basic-offset] 6 (#$ . 177102) nil]) #@45 Insert a component instantiation statement. (defalias 'vhdl-template-component-inst #[nil "\306 `\307\211\310\311\307\312\n`%\205\277�\313c\210\314\314 @=\206(�\f \211%A@)>)\2033�\310\315!\210\202\207�\310\316\317\312#\211\206>�\320\226\211\321\232\203k�\310\322\323\307\211\211\211\324&\210\310\325\326\"\210\310\327\307\312#\203d�\330c\210\202\207�\331\332!\210\202\207� \333\232\203\203�\310\322\323\307\211\211\211\324&\210\310\334!\210\202\207�\310\315!\210\335c\210 &\\j\210`\336\337!\210\340\312\211#\203\247�\335c\210 &\\j\210`\336\341!\210\340\312\211#\204\275�\342\343!\210\331\332!\210\344c,\207" [position unit start margin standard vhdl-standard current-indentation nil vhdl-template-field "instance label" t ": " 87 "component name" "[COMPONENT | ENTITY | CONFIGURATION]" " " "" "ENTITY" "library name" "." "work" "entity name" "(" "[architecture name]" ")" delete-char -1 "CONFIGURATION" "configuration name" "\n" vhdl-insert-keyword "GENERIC " vhdl-template-map "PORT " kill-line 0 ";" x vhdl-basic-offset] 9 (#$ . 177725) nil]) #@41 Insert a conditional signal assignment. (defalias 'vhdl-template-conditional-signal-asst #[nil "\305\306!\205d�\307c\210i`\310\305\311!\210`\312\313!\210 \203 �\314c\210\305\315\310\316#\203S� \203/�\317c\210`\312\320!\210\321c\210\nj\210\305\322\310\316#\203S�`\312\313!\210 \203 �\314c\210\202 �`|\210\323c\210\f\205c�\324 `\325#+\207" [position start margin vhdl-conditions-in-parenthesis vhdl-auto-align vhdl-template-field "target signal" " <= " nil "waveform" vhdl-insert-keyword " WHEN " "(" "[condition]" t ")" " ELSE" "\n" "[waveform]" ";" vhdl-align-noindent-region 1] 4 (#$ . 178792) nil]) #@196 Insert a configuration specification if within an architecture, a block or component configuration if within a configuration declaration, a configuration declaration if not within a design unit. (defalias 'vhdl-template-configuration #[nil "\304\305\306\307\310\n#\210\212\311\312\305\304#)\203\"�\313\314!\226\315\232\203\"�\316 \202K�\212\311\317\305\304#)\203I�\313\314!\226\320\232\203I�\321\322\323\304#\324=\203D�\325 \202K�\326 \202K�\327  \204V�\306\307\330\n#\210 *\207" [case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-backward "^\\(architecture\\|end\\)\\>" match-string 1 "ARCHITECTURE" vhdl-template-configuration-spec "^\\(configuration\\|end\\)\\>" "CONFIGURATION" vhdl-decision-query "configuration" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration vhdl-template-configuration-decl "_"] 4 (#$ . 179407) nil]) #@39 Insert a configuration specification. (defalias 'vhdl-template-configuration-spec #[(&optional optional-use) "\306 `\307\211\310\311!\210\312\313\314\315\n`%\205\330�\312\316\317\"\210 \f\\j\210`\310\320!\210 \203=�\312\321\322\315#\211\204=�\n`|\210\323\202\330� \204F�\312\324\322\" \206K�\325\226\211\326\232\203\270�\312\327\330\307\211\211\211\331&\210\312\332\333\"\210\312\334\307\315#\203q�\335c\210\202u�\336\337!\210\317c\210 \f\211\\\340\\\\j\210`\310\341!\210\342\315\211#\203\233�\317c\210 \f\211\\\340\\\\j\210`\310\343!\210\342\315\211#\204\261�\344\340!\210\336\337!\210\345c\210\315\202\330� \346\232\203\320�\312\327\330\307\211\211\211\331&\210\312\347\345\"\202\330�\350\351!\210\345c\210\315,\207" [position aspect start margin vhdl-basic-offset optional-use current-indentation nil vhdl-insert-keyword "FOR " vhdl-template-field "component names | OTHERS | ALL" " : " t "component type" "\n" "USE " "[ENTITY | CONFIGURATION | OPEN]" " " no-use "ENTITY | CONFIGURATION | OPEN" "" "ENTITY" "library name" "." "work" "entity name" "(" "[architecture name]" ")" delete-char -1 0 "GENERIC " vhdl-template-map "PORT " kill-line ";" "CONFIGURATION" "configuration name" backward-delete-char 1] 9 (#$ . 180372) nil]) #@37 Insert a configuration declaration. (defalias 'vhdl-template-configuration-decl #[nil "\306 `\307\310\211\211\211\311\312!\210\313\314\310\307 `%\211\205\261�\311\315!\210\212\310 \316\317\320!#\210\321\322\310\307#\323\324!\211 \"\204H�\316\317\325!#\210 \210* \203\\�\n\326\232\204\\�\nc\210\202`�\313\327!\210\311\330!\210#\331>\203n�\332c\210$\\j\210`\332c\210#\333>\203\204�\332c\210j\210\311\334!\210\335%\335&@=\206\242�%&\211'A@)>)\204\252�\311\312!\210 \336\261\210b.\207" [position name string entity-exists case-fold-search start current-indentation t nil vhdl-insert-keyword "CONFIGURATION " vhdl-template-field "name" " OF " modify-syntax-entry 95 "w" re-search-backward "\\<entity \\(\\w*\\) is\\>" match-string 1 "_" "" "entity name" " IS\n" (unit all) "\n" (unit all) "END " 87 ";" margin result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word vhdl-insert-empty-lines vhdl-basic-offset standard vhdl-standard x] 7 (#$ . 181623) nil]) #@32 Insert a constant declaration. (defalias 'vhdl-template-constant #[nil "`\303 \304\305!\210\306\307\310\311 `%\205E�\312c\210\203�\304\313!\210\306\314!\210\203.�\315c\210\316 \202E�`\317c\210\306\320\310\311#\204?�\n`|\210\315c\210\316 )*\207" [in-arglist start position vhdl-in-argument-list-p vhdl-insert-keyword "CONSTANT " vhdl-template-field "name" nil t " : " "IN " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 6 (#$ . 182619) nil]) #@17 Insert nothing. (defalias 'vhdl-template-default #[nil "\300c\210\301 \210\302v\210\303\304!\210\304u\207" [" " unexpand-abbrev -1 vhdl-case-word 1] 2 (#$ . 183091) nil]) #@28 Insert nothing and indent. (defalias 'vhdl-template-default-indent #[nil "\300c\210\301 \210\302v\210\303\304!\210\304u\210\305 \207" [" " unexpand-abbrev -1 vhdl-case-word 1 vhdl-indent-line] 2 (#$ . 183268) nil]) #@32 Insert a disconnect statement. (defalias 'vhdl-template-disconnect #[nil "`\301\302!\210\303\304\305\306`%\205�\303\307!\210\301\310!\210\303\311\312\")\207" [start vhdl-insert-keyword "DISCONNECT " vhdl-template-field "signal names | OTHERS | ALL" " : " t "type" " AFTER " "time expression" ";"] 6 (#$ . 183489) nil]) #@27 Insert an else statement. (defalias 'vhdl-template-else #[nil "\306\307\307\310\311\312 #\210\313\314!\210\212\315\316\307\306#\210\317\320!\226\321\232)\203&�\322c\2023�\323 \210\324 \325c\210\f\\j \204>�\310\311\326 #\210\n+\207" [margin case-fold-search result vhdl-mode-syntax-table vhdl-basic-offset vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" vhdl-insert-keyword "ELSE" re-search-backward "\\(\\<when\\>\\|;\\)" match-string 1 "WHEN" " " vhdl-indent-line current-indentation "\n" "_"] 4 (#$ . 183817) nil]) #@28 Insert an elsif statement. (defalias 'vhdl-template-elsif #[nil "`\304\305\306!\210\n\203�\307c\210\310\311\304\312 `%\205:�\n\203 �\313c\210\314 \210\315 \305\316\317 \2031�\320\2022�\321\322Q!\210 \\j*\207" [margin start vhdl-conditions-in-parenthesis vhdl-basic-offset nil vhdl-insert-keyword "ELSIF " "(" vhdl-template-field "condition" t ")" vhdl-indent-line current-indentation " " vhdl-sequential-statement-p "THEN" "USE" "\n"] 6 (#$ . 184363) nil]) #@19 Insert an entity. (defalias 'vhdl-template-entity #[nil "\306 `\307\211\310\311!\210\312\313\307\314\n`%\211\205\215�\310\315!\210 j\210\310\316!\210\317\317 @=\2066�\f \211A@)>)\204>�\310\311!\210 \320\261\210i\321\210 \\j\210\322>\203X�\323c\210 \\j\210\324\314!\203n�\325>\203n�\323c\210\323c\210 \\j\210\326\314!\203\207�\327>\203\207�\323c\210\330\331!\210u,\207" [end-column name start margin standard vhdl-standard current-indentation nil vhdl-insert-keyword "ENTITY " vhdl-template-field "name" t " IS\n\n" "END " 87 ";" 0 (unit all) "\n" vhdl-template-generic-list (unit all) vhdl-template-port-list (unit all) beginning-of-line 2 x vhdl-basic-offset vhdl-insert-empty-lines] 6 (#$ . 184831) nil]) #@27 Insert an exit statement. (defalias 'vhdl-template-exit #[nil "`\303\304!\210\305\306\307\310#\204�\311\312!\210`\303\313!\210\n\203�\314c\210\305\315\307\310#\2031�\n\2035�\316c\210\2025� `|\210)\317c)\207" [start position vhdl-conditions-in-parenthesis vhdl-insert-keyword "EXIT " vhdl-template-field "[loop label]" nil t delete-char -1 " WHEN " "(" "[condition]" ")" ";"] 4 (#$ . 185568) nil]) #@28 Insert a file declaration. (defalias 'vhdl-template-file #[nil "`\304\305!\210\306\307\310\311`%\205j�\312c\210\306\313!\210\314\314\n@=\206(� \n\211A@)>)\204<�\304\315!\210\306\316\310\311#\204<�\317\320!\210\304\321!\210\314\314\n@=\206Q� \n\211A@)>)\203[�\306\322\323\311#\210\306\324\310\211\211\211\311&\210\325c\210\326 )\207" [start standard vhdl-standard x vhdl-insert-keyword "FILE " vhdl-template-field "name" nil t " : " "type" 87 " OPEN " "[READ_MODE | WRITE_MODE | APPEND_MODE]" backward-delete-char 6 " IS " "[IN | OUT]" " " "filename-string" ";" vhdl-comment-insert-inline] 7 (#$ . 185975) nil]) #@212 Insert a block or component configuration if within a configuration declaration, a configuration specification if within an architecture declarative part (and not within a subprogram), and a for-loop otherwise. (defalias 'vhdl-template-for #[nil "\304\305\306\307\310\n#\210\212\311\312\305\304#)\2031�\313\314!\226\315\232\2031�\316\317\320\304#\321=\203,�\322 \202r�\323 \202r�\212\311\324\305\304#)\203f�\313\314!\226\325\232\203f�\212\311\326\305\304#)\203a�\313\314!\226\327\232\203a�\212\311\330\305\304#)\204f�\331 \202r�\332 \203p�\333 \202r�\334  \204}�\306\307\335\n#\210 *\207" [case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-backward "^\\(configuration\\|end\\)\\>" match-string 1 "CONFIGURATION" vhdl-decision-query "for" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration "^\\(architecture\\|entity\\|begin\\|end\\)\\>" "ARCHITECTURE" "^\\s-*\\(architecture\\|begin\\|end\\)\\>" "BEGIN" "^\\s-*\\(function\\|procedure\\)\\>" vhdl-template-configuration-spec vhdl-sequential-statement-p vhdl-template-for-loop vhdl-template-for-generate "_"] 4 (#$ . 186600) nil]) #@24 Insert a for-generate. (defalias 'vhdl-template-for-generate #[nil "\305 `\306\211\211\307\310!\210\311  b\210\312\313\306\314 %\211\2054�b\210\312\315!\210\307\316!\210\312\317!\210\320\f\n\"-\207" [position string label start margin current-indentation nil vhdl-insert-keyword ": FOR " point-marker vhdl-template-field "label" t "loop variable" " IN " "range" vhdl-template-generate-body] 6 (#$ . 187816) nil]) #@20 Insert a for loop. (defalias 'vhdl-template-for-loop #[nil "\306 `\307\211\f\310=\204�\311\312!\210\2021�\311\313!\210\nb\210\314\315\307\316#\211\204+�\317\320!\210\321v\210\321u\210\314\322\307\316\n`%\211\205q�\311\323!\210\314\324!\210\311\325!\210 j\210\311\326!\210 \203]�\327 \330\261\210\202i�\330c\210 \203i�\331\261\210\332y\210 \\j,\207" [index label start margin vhdl-optional-labels vhdl-self-insert-comments current-indentation nil all vhdl-insert-keyword "FOR " ": FOR " vhdl-template-field "[label]" t delete-char 2 1 "loop variable" " IN " "range" " LOOP\n\n" "END LOOP" " " ";" " -- " -1 vhdl-basic-offset] 7 (#$ . 188244) nil]) #@28 Insert a VHDL file footer. (defalias 'vhdl-template-footer #[nil "\301\232?\205�\212db\210\302c\210\303!)\207" [vhdl-file-footer "" "\n" vhdl-insert-string-or-file] 2 (#$ . 188910) nil]) #@40 Insert a function declaration or body. (defalias 'vhdl-template-function #[(&optional kind) "\306 `\307\310\311!\210\312\313\307\314 `%\211\205w�\315\314!\210 \203%�\316 `\317#\210\307\210\320c\210\n\f\\j\210\310\321!\210\312\322!\210 \203B� \323=\202H�\324\307\325\"\326=\203u�\310\327!\210\330\331\331@=\206f�\211A@)>)?\205l�\332\n#\210\333 \202w�\334c+\207" [name start margin vhdl-auto-align vhdl-basic-offset kind current-indentation nil vhdl-insert-keyword "FUNCTION " vhdl-template-field "name" t vhdl-template-argument-list vhdl-align-noindent-region 1 "\n" "RETURN " "type" body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS" vhdl-template-begin-end 87 "FUNCTION" vhdl-comment-block ";" standard vhdl-standard x] 6 (#$ . 189106) nil]) #@32 Insert a function declaration. (defalias 'vhdl-template-function-decl #[nil "\300\301!\207" [vhdl-template-function decl] 2 (#$ . 189881) nil]) #@32 Insert a function declaration. (defalias 'vhdl-template-function-body #[nil "\300\301!\207" [vhdl-template-function body] 2 (#$ . 190031) nil]) #@29 Insert a generation scheme. (defalias 'vhdl-template-generate #[nil "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(f)or or (i)f?" t 105 vhdl-template-if-generate vhdl-template-for-generate] 4 (#$ . 190181) nil]) #@73 Insert generic declaration, or generic map in instantiation statements. (defalias 'vhdl-template-generic #[nil "`\305\306\307\310\311 #\210\212\312\313\306\305#)\203%�\314\315!\226\316\232\203%�\317\306!\202I�\212\320 \206.�\321\322!)\204;�\323 @@\324\232\203E�\325\326!\210\327 !\202I�\317\306\305\"\f\204T�\307\310\330 #\210\n+\207" [case-fold-search start result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-backward "^\\(entity\\|end\\)\\>" match-string 1 "ENTITY" vhdl-template-generic-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "GENERIC " vhdl-template-map "_"] 4 (#$ . 190428) nil]) #@45 Insert group or group template declaration. (defalias 'vhdl-template-group #[nil "`\301\302\303\304#\305=\203�\306 \202�\307 )\207" [start vhdl-decision-query "group" "(d)eclaration or (t)emplate declaration?" t 116 vhdl-template-group-template vhdl-template-group-decl] 4 (#$ . 191162) nil]) #@27 Insert group declaration. (defalias 'vhdl-template-group-decl #[nil "`\301\302!\210\303\304\305\306`%\205�\303\307\310\"\210\303\311\312\"\210\313 )\207" [start vhdl-insert-keyword "GROUP " vhdl-template-field "name" " : " t "template name" " (" "constituent list" ");" vhdl-comment-insert-inline] 6 (#$ . 191464) nil]) #@36 Insert group template declaration. (defalias 'vhdl-template-group-template #[nil "`\301\302!\210\303\304\305\306`%\205�\301\307!\210\303\310\311\"\210\312 )\207" [start vhdl-insert-keyword "GROUP " vhdl-template-field "template name" nil t " IS (" "entity class list" ");" vhdl-comment-insert-inline] 6 (#$ . 191793) nil]) #@28 Insert a VHDL file header. (defalias 'vhdl-template-header #[nil "\306\232?\205|\307\310 \n\"@\206�\306\311\310 \n\"8\206�\306\312.\312/\313\314\3150#\210\212\214~\210eb\210\316!\210`e }\210eb\210\317\320\312\307#\203P�\321\f\307\211#\210\202?�eb\210\317\322\312\307#\203e�\321\323 \307\211#\210\202S�eb\210\317\324\312\307#\203\211�\321\306\307\211#\210\325 c\2101\203h�\3261\327\261\210\202h�eb\210\317\330\312\307#\203\236�\321\331 \307\211#\210\202\214�eb\210\317\332\312\307#\203\262�\321 \307\211#\210\202\241�eb\210\317\333\312\307#\203\307�\3212\307\211#\210\202\265�eb\210\317\334\312\307#\203\334�\3213\307\211#\210\202\312�eb\210\317\335\312\307#\203\360�\321\336\312\307#\210\202\337�eb\210\317\337\312\307#\203\321\306\307\211#\210\340 \210\202\363�eb\210\3124\341\342\312\307#\203(\343\344\345!\346P!4\3214\307\211#\210\202 +eb\210\317\347\312\307#\203:\321\306\307\211#\210 \203D \306\232\203H\350\351!\210\f\203R\f\306\232\203V\350\352!\2102\306\232\203a\350\353!\2103\306\232\205k\350\354!/5\204y\313\314\3550#\210/-\207" [vhdl-file-header vhdl-project-alist vhdl-project eot project-desc project-name "" t aget 2 nil modify-syntax-entry 95 "w" vhdl-insert-string-or-file search-forward "<projectdesc>" replace-match "<filename>" buffer-name "<author>" user-full-name " <" ">" "<login>" user-login-name "<project>" "<company>" "<platform>" "<RCS>" "$" "<date>" vhdl-template-insert-date re-search-forward "<\\(\\(\\w\\|\\s_\\)*\\) string>" read-string match-string 1 ": " "<cursor>" message "You can specify a project title in custom variable `vhdl-project-alist'" "You can specify a project description in custom variable `vhdl-project-alist'" "You can specify a company name in custom variable `vhdl-company-name'" "You can specify a platform in custom variable `vhdl-platform-spec'" "_" case-fold-search result vhdl-mode-syntax-table user-mail-address vhdl-company-name vhdl-platform-spec string vhdl-underscore-is-part-of-word] 6 (#$ . 192125) nil]) #@63 Insert a sequential if statement or an if-generate statement. (defalias 'vhdl-template-if #[nil "\303 \203�\304 \207\305\305 @=\206� \211A@)>)\203*�\306\307\310\311#\312=\203*�\313 \207\314 \207" [standard vhdl-standard x vhdl-sequential-statement-p vhdl-template-if-then ams vhdl-decision-query "if" "(g)enerate or (u)se?" t 117 vhdl-template-if-use vhdl-template-if-generate] 4 (#$ . 194141) nil]) #@24 Insert an if-generate. (defalias 'vhdl-template-if-generate #[nil "\306 `\307\211\211\310\311!\210\312  b\210\313\314\307\315 %\211\205:�b\210 \203+�\316c\210\313\317!\210 \2036�\320c\210\321\f\n\"-\207" [position string label start margin vhdl-conditions-in-parenthesis current-indentation nil vhdl-insert-keyword ": IF " point-marker vhdl-template-field "label" t "(" "condition" ")" vhdl-template-generate-body] 6 (#$ . 194552) nil]) #@35 Insert a sequential if statement. (defalias 'vhdl-template-if-then-use #[(kind) "\306 `\307 \310=\203#�\311\311 @=\206�\f \211A@)>)\203*�\312\313!\210\202E�\312\314!\210 b\210\315\316\307\317#\211\204?�\320\321!\210\322v\210\322u\210\203M�\323c\210\315\324\307\317 `%\205\214�\203_�\325c\210\312\326 \327=\203l�\330\202m�\331\332Q!\210\nj\210\312\333!\210\203\201�\326\261\210\334c\210\335y\210\n!\\j+\207" [label start margin vhdl-optional-labels standard vhdl-standard current-indentation nil all 87 vhdl-insert-keyword "IF " ": IF " vhdl-template-field "[label]" t delete-char 2 1 "(" "condition" ")" " " then "THEN" "USE" "\n\n" "END IF" ";" -1 x vhdl-conditions-in-parenthesis kind vhdl-basic-offset] 7 (#$ . 195004) nil]) #@35 Insert a sequential if statement. (defalias 'vhdl-template-if-then #[nil "\300\301!\207" [vhdl-template-if-then-use then] 2 (#$ . 195755) nil]) #@37 Insert a simultaneous if statement. (defalias 'vhdl-template-if-use #[nil "\300\301!\207" [vhdl-template-if-then-use use] 2 (#$ . 195905) nil]) #@45 Insert a component instantiation statement. (defalias 'vhdl-template-instance #[nil "\300 \207" [vhdl-template-component-inst] 1 (#$ . 196055) nil]) #@33 Insert a library specification. (defalias 'vhdl-template-library #[nil "\304 `\305\211\306\307!\210\310\311\305\312\n`%\211\205J�\313c\210\314\315 \"?\205J�`\316c\210 j\210\306\317!\210 c\210\306\320!\210\321u\210\310\322!\203E�\323u\202J�`\323\\|,\207" [end-pos name start margin current-indentation nil vhdl-insert-keyword "LIBRARY " vhdl-template-field "names" t ";" string-match "," "\n" "USE " "..ALL;" -5 "package name" 5] 6 (#$ . 196210) nil]) #@17 Insert a limit. (defalias 'vhdl-template-limit #[nil "`\301\302!\210\303\304\305\306`%\205�\303\307!\210\301\310!\210\303\311\312\")\207" [start vhdl-insert-keyword "LIMIT " vhdl-template-field "quantity names | OTHERS | ALL" " : " t "type" " WITH " "real expression" ";"] 6 (#$ . 196674) nil]) #@16 Insert a loop. (defalias 'vhdl-template-loop #[nil "\301\302\303\304#\211\305=\203�\306 \202�\307=\203�\310 \202�\311 )\207" [char vhdl-decision-query nil "(w)hile, (f)or, or (b)are?" t 119 vhdl-template-while-loop 102 vhdl-template-for-loop vhdl-template-bare-loop] 5 (#$ . 196978) nil]) #@16 Insert a loop. (defalias 'vhdl-template-bare-loop #[nil "\305 `\306 \307=\204�\310\311!\210\2020�\310\312!\210 b\210\313\314\306\315#\211\204)�\316\317!\210\320v\210\316\320!\210\321c\210\nj\210\310\322!\210\203E�\323\324Q\202F�\324c\210\325y\210\n\f\\j+\207" [label start margin vhdl-optional-labels vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "LOOP " ": LOOP " vhdl-template-field "[label]" t delete-char 2 1 "\n\n" "END LOOP" " " ";" -1] 5 (#$ . 197279) nil]) #@51 Insert a map specification with association list. (defalias 'vhdl-template-map #[(&optional start optional secondary) "\206�`\306\211\307\310!\210 \204E�\311\f\205�\312\313\f\205�\314Q\315 ?\206&�\f ?\205,�`%\2035�\316\202\306�\f\203A� \203A�`|\210\306\202\306�\203O�i\202[�\317 \\\320c\210\nj\210\311\f\205a�\312\321\f\205g�\314Q\322 ?\206o�\f ?\205u�`%\203\271�\311\323\324\"\210`\320c\210\nj\210\311\325\322\316#\203\237�\311\323\324\"\210`\320c\210\nj\210\202\207� `|\210\326\327!\210\315c\210\203\265�\330`\327#\210\316\202\306�\f\203\305� \203\305�`|\210\306+\207" [start end-pos margin vhdl-association-list-with-formals optional secondary nil vhdl-insert-keyword "MAP (" vhdl-template-field "[" "association list" "]" ")" t current-indentation "\n" "formal" " => " "actual" "," "[formal]" backward-delete-char 1 vhdl-align-noindent-region vhdl-argument-list-indent vhdl-basic-offset vhdl-auto-align] 6 (#$ . 197777) nil]) #@30 Actualize modification date. (defalias 'vhdl-template-modify #[(&optional noerror) "\306\307\310\311\312\n#\210\212eb\210\313 \307\306#\203�\314 \210\315 \202)�\f?\205)�\316\317 \320Q!) \2045�\310\311\321\n#\210 *\207" [case-fold-search result vhdl-mode-syntax-table vhdl-modify-date-prefix-string noerror vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-forward kill-line vhdl-template-insert-date error "Modification date prefix string \"" "\" not found" "_"] 4 (#$ . 198735) nil]) #@51 Call `vhdl-template-modify' with NOERROR non-nil. (defalias 'vhdl-template-modify-noerror #[nil "\300\301!\207" [vhdl-template-modify t] 2 (#$ . 199255)]) #@30 Insert a nature declaration. (defalias 'vhdl-template-nature #[nil "`\305\211\211\306\307!\210\310\311\305\312 `%\211\205\204�\306\313!\210\310\314!\206#�\315\226\211\315\232\2031�\316c\210\202m�\f\317\232\203C�\320\321!\210\322\323\312\"\210\202m�\f\324\232\203Y�\325 \320\321!\210\326\323\n\312#\210\202m�\306\327!\210\310\330!\210\306\331!\210\310\332!\210\306\333!\210 \203z�\325  b\210\305\210\334 \210\205\203�b),\207" [end-pos mid-pos name start definition nil vhdl-insert-keyword "NATURE " vhdl-template-field "name" t " IS " "across type | ARRAY | RECORD" "" ";" "ARRAY" kill-word -1 vhdl-template-array nature "RECORD" point-marker vhdl-template-record " ACROSS " "through type" " THROUGH " "reference name" " REFERENCE;" vhdl-comment-insert-inline] 7 (#$ . 199416) nil]) #@26 Insert a next statement. (defalias 'vhdl-template-next #[nil "\302\303!\210\304\305\306\307#\204�\310\311!\210`\302\312!\210 \203�\313c\210\304\314\306\307#\203/� \2033�\315c\210\2023�`|\210\316c)\207" [position vhdl-conditions-in-parenthesis vhdl-insert-keyword "NEXT " vhdl-template-field "[loop label]" nil t delete-char -1 " WHEN " "(" "[condition]" ")" ";"] 4 (#$ . 200215) nil]) #@29 Insert an others aggregate. (defalias 'vhdl-template-others #[nil "\300\301!\210\302u\207" [vhdl-insert-keyword "(OTHERS => '')" -2] 2 (#$ . 200610) nil]) #@41 Insert a package specification or body. (defalias 'vhdl-template-package #[(&optional kind) "\306 `\307\211\211\310\311!\210 \203� \301=\202�\312\307\313\"\314=\211\203(�\310\315!\210\316\317\307\320 `%\211\205\215�\310\321!\210\322>\203B�\323c\210\f\\j\210`\323c\210\324>\203W�\323c\210\fj\210\310\325!\210\326\326@=\206t�\211A@)>)\204\202�\310\311 \205�\315P!\210\n\206\207�\327\330\261\210b-\207" [position body name start margin kind current-indentation nil vhdl-insert-keyword "PACKAGE " vhdl-decision-query "(d)eclaration or (b)ody?" 98 "BODY " vhdl-template-field "name" t " IS\n" (unit all) "\n" (unit all) "END " 87 "" ";" vhdl-insert-empty-lines vhdl-basic-offset standard vhdl-standard x] 7 (#$ . 200771) nil]) #@33 Insert a package specification. (defalias 'vhdl-template-package-decl #[nil "\300\301!\207" [vhdl-template-package decl] 2 (#$ . 201528) nil]) #@24 Insert a package body. (defalias 'vhdl-template-package-body #[nil "\300\301!\207" [vhdl-template-package body] 2 (#$ . 201677) nil]) #@69 Insert a port declaration, or port map in instantiation statements. (defalias 'vhdl-template-port #[nil "`\305\306\307\310\311 #\210\212\312\313\306\305#)\203%�\314\315!\226\316\232\203%�\317\306!\202H�\212\320 \206.�\321\322!)\204;�\323 @@\324\232\203E�\325\326!\210\327 !\202H�\317\306!\f\204S�\307\310\330 #\210\n+\207" [case-fold-search start result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-backward "^\\(entity\\|end\\)\\>" match-string 1 "ENTITY" vhdl-template-port-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "PORT " vhdl-template-map "_"] 4 (#$ . 201817) nil]) #@22 Insert a procedural. (defalias 'vhdl-template-procedural #[nil "\306 `\307\310\311\312!\210\f\313>\2030�\nb\210\314c\210\nb\210\315\316\310\307#\211\204*�\317\320!\210\321v\210\321u\210\322\322@=\206D� \211A@)>)\204L�\311\323!\210\324\325 #\210\326 ,\207" [label case-fold-search start margin vhdl-optional-labels standard current-indentation t nil vhdl-insert-keyword "PROCEDURAL " (process all) ": " vhdl-template-field "[label]" delete-char 2 1 87 "IS" vhdl-template-begin-end "PROCEDURAL" vhdl-comment-block vhdl-standard x] 5 (#$ . 202533) nil]) #@41 Insert a procedure declaration or body. (defalias 'vhdl-template-procedure #[(&optional kind) "\306 `\307\310\311!\210\312\313\307\314 `%\211\205q�\315 \210 \203$� \316=\202*�\317\307\320\"\321=\203b�\310\322!\210\f\203;�\323 `\324#\210\307\210\325\326\326@=\206S� \211A@)>)?\205Y�\327\n#\210\330 \202q�\331c\210\f\203o�\323 `\324#\210\307+\207" [name start margin kind vhdl-auto-align standard current-indentation nil vhdl-insert-keyword "PROCEDURE " vhdl-template-field "name" t vhdl-template-argument-list body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS" vhdl-align-noindent-region 1 vhdl-template-begin-end 87 "PROCEDURE" vhdl-comment-block ";" vhdl-standard x] 6 (#$ . 203103) nil]) #@33 Insert a procedure declaration. (defalias 'vhdl-template-procedure-decl #[nil "\300\301!\207" [vhdl-template-procedure decl] 2 (#$ . 203823) nil]) #@26 Insert a procedure body. (defalias 'vhdl-template-procedure-body #[nil "\300\301!\207" [vhdl-template-procedure body] 2 (#$ . 203976) nil]) #@19 Insert a process. (defalias 'vhdl-template-process #[(&optional kind) "\306 `\307\310\211\211\211\211\211:;<=\203\"�=\304=\202)�\311\312\313\307#\314=\315\316!\210>\317>\203T�;b\210\320c\210;b\210\321\322\310\307#\211\204N�\323\324!\210\325v\210\325u\210\326c\210\f\204n�\321\327\330\307#\211\204\253�\331\323\332!\210\202\253�?\331\232\204~�?c\210?\206\205�\321\333!\206\205�\334@\335=\203\250�\336c\210A\331\232\204\240�Ac\210A\206\247�\321\337!\206\247�\340\330c\210\341B\341C@=\206\301�BC\211DA@)>)\204\311�\315\342!\210\343\344 <#\210\f\203\331�\345\n \"E\205\207\346 \310F\347\350\351G#\210\352\353\310\307#\205s\352\354\310\307#\205s\355\210o\203 \356c\210\357y\210\202\356c\210<j\210\360c\210\321\361\310\307#\204\"\362 \202s\356c\210<j\210\363c\210\f\2034\364\2025\365\356\261\210<j\210\366c\210\f\204J c\210\202d\n\336\261\210 \203X \336\261\210\321\367\310\307#\204d\323\332!\210\356c\210<j\210\370c\210\321\367\310\307#FH\204\201\347\350\371G#\210F\210)b. \207" [final-pos reset clock input-signals seq label current-indentation t nil vhdl-decision-query "process" "(c)ombinational or (s)equential?" 115 vhdl-insert-keyword "PROCESS " (process all) ": " vhdl-template-field "[label]" delete-char 2 1 "(" "[sensitivity list]" ")" "" -2 "clock name" "<clock>" async ", " "reset name" "<reset>" 87 " IS" vhdl-template-begin-end "PROCESS" vhdl-template-seq-process point-marker modify-syntax-entry 95 "w" re-search-backward "\\<begin\\>" "\\<process\\>" 0 "\n" -1 "-- purpose: " "[description]" vhdl-line-kill-entire "-- type : " "sequential" "combinational" "-- inputs : " "[signal names]" "-- outputs: " "_" case-fold-search start margin kind vhdl-optional-labels vhdl-clock-name vhdl-reset-kind vhdl-reset-name standard vhdl-standard x vhdl-prompt-for-comments result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word] 10 (#$ . 204122) nil]) #@33 Insert a combinational process. (defalias 'vhdl-template-process-comb #[nil "\300\301!\207" [vhdl-template-process comb] 2 (#$ . 206054) nil]) #@30 Insert a sequential process. (defalias 'vhdl-template-process-seq #[nil "\300\301!\207" [vhdl-template-process seq] 2 (#$ . 206203) nil]) #@32 Insert a quantity declaration. (defalias 'vhdl-template-quantity #[nil "\302 \203)�`\303\304!\210\305\306\307\310`%\205'�\311c\210\305\312\313\310#\210\305\314!\210\315c\210\316 )\207\317\320\321\310#\211\322=\203:�\323 \202T� \324=\203E�\325 \202T� \326=\203P�\327 \202T�\330``\")\207" [start char vhdl-in-argument-list-p vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" nil t " : " "[IN | OUT]" " " "type" ";" vhdl-comment-insert-inline vhdl-decision-query "quantity" "(f)ree, (b)ranch, or (s)ource quantity?" 102 vhdl-template-quantity-free 98 vhdl-template-quantity-branch 115 vhdl-template-quantity-source vhdl-template-undo] 7 (#$ . 206347) nil]) #@37 Insert a free quantity declaration. (defalias 'vhdl-template-quantity-free #[nil "\301\302!\210\303\304!\210\305c\210\303\306!\210`\307c\210\303\310\311\312#\204 �`|\210\313c\210\314 )\207" [position vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " := " "[initialization]" nil t ";" vhdl-comment-insert-inline] 4 (#$ . 207020) nil]) #@39 Insert a branch quantity declaration. (defalias 'vhdl-template-quantity-branch #[nil "\301\302\303!\210\304\305\306\307#\203�\302\310!\210\304\311\306\307#\203�\302\312!\210\304\313!\210`\302\314!\210\304\315\301\307#\2044�`|\210\316c\210\317 )\207" [position nil vhdl-insert-keyword "QUANTITY " vhdl-template-field "[across names]" " " t "ACROSS " "[through names]" "THROUGH " "plus terminal name" " TO " "[minus terminal name]" ";" vhdl-comment-insert-inline] 4 (#$ . 207387) nil]) #@39 Insert a source quantity declaration. (defalias 'vhdl-template-quantity-source #[nil "\300\301!\210\302\303!\210\304c\210\302\305\306\"\210\307\310\311\"\312=\203$�\300\313!\210\302\314!\210\2021�\300\315!\210\302\316\317\"\210\302\320!\210\321c\210\322 \207" [vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " " vhdl-decision-query nil "(s)pectrum or (n)oise?" 110 "NOISE " "power expression" "SPECTRUM " "magnitude expression" ", " "phase expression" ";" vhdl-comment-insert-inline] 3 (#$ . 207882) nil]) #@35 Insert a record type declaration. (defalias 'vhdl-template-record #[(kind &optional name secondary) "i`\306\307\310!\210\n \\j\210\311\312\313\f? `%\204�\f\205\212�\204*�\311\314\313\306#\203M�\315c\210\311 \316=\2038�\317\2029�\320\321\"\210\322 \210\323c\210\n \\j\210\313\211\202�\324\325!\210\nj\210\307\326!\210\327\327@=\206n�\211A@)>)\204}�\203}�\330\261\210\321c\210\205\212�\331 `\332#+\207" [first start margin vhdl-basic-offset secondary kind t vhdl-insert-keyword "RECORD\n" vhdl-template-field "element names" nil "[element names]" " : " type "type" "nature" ";" vhdl-comment-insert-inline "\n" kill-line 0 "END RECORD" 87 " " vhdl-align-noindent-region 1 standard vhdl-standard x name vhdl-auto-align] 7 (#$ . 208420) nil]) #@28 Insert a report statement. (defalias 'vhdl-template-report #[nil "`\301\302!\210\303\304\305\306`\306&\307\232\203�\310\311!\202.�`\301\312!\210\303\313\305\306#\204,�`|\210\314c)\207" [start vhdl-insert-keyword "REPORT " vhdl-template-field "string expression" nil t "\"\"" backward-delete-char 2 " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 7 (#$ . 209188) nil]) #@28 Insert a return statement. (defalias 'vhdl-template-return #[nil "\300\301!\210\302\303\304\305#\204�\306\307!\210\310c\207" [vhdl-insert-keyword "RETURN " vhdl-template-field "[expression]" nil t delete-char -1 ";"] 4 (#$ . 209575) nil]) #@38 Insert a selected signal assignment. (defalias 'vhdl-template-selected-signal-asst #[nil "\306 `\307`\310\311!\210 b\210)\310\312!\210\313\314\315\307 `\316\\%\205\225�\317v\210\320\317!\210\321c\210\n\f\\j\210\313\322\323\"\210\321c\210\n\f\\j\210\313\324!\210\310\325!\210\313\326\327\"\210\321c\210\n\f\\j\210\203~�\313\330\315\307#\203~�\310\325!\210\313\331\327\307#\211\203w�\321c\210\n\f\\j\210\202R�\310\332!\210\202R�\203\211�\333 \210\320\334!\210\335c\210 \205\225�\336 `\317#+\207" [choices start margin position vhdl-basic-offset vhdl-auto-align current-indentation t vhdl-insert-keyword " SELECT " "WITH " vhdl-template-field "selector expression" nil 7 1 delete-char "\n" "target signal" " <= " "waveform" " WHEN " "choices" "," "[waveform]" "[choices]" "OTHERS" fixup-whitespace -2 ";" vhdl-align-noindent-region] 7 (#$ . 209821) nil]) #@30 Insert a signal declaration. (defalias 'vhdl-template-signal #[nil "`\303 \304\305!\210\306\307\310\311 `%\205G�\312c\210\203 �\306\313\314\311#\210\306\315!\210\2030�\316c\210\317 \202G�`\320c\210\306\321\310\311#\204A�\n`|\210\316c\210\317 )*\207" [in-arglist start position vhdl-in-argument-list-p vhdl-insert-keyword "SIGNAL " vhdl-template-field "names" nil t " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 6 (#$ . 210686) nil]) #@33 Insert a subnature declaration. (defalias 'vhdl-template-subnature #[nil "`\302\303\304!\210\305\306\302\307 `%\205_�\303\310!\210\305\311\312\"\210\305\313\302\307#\203)�\314c\210\202-�\315\316!\210`\303\317!\210\305\320\302\307\302\211\307&\321\232\203H�`|\210\202Z�\303\322!\210\305\323\302\211\211\211\307&\210\303\324!\210\325c\210\326 *\207" [position start nil vhdl-insert-keyword "SUBNATURE " vhdl-template-field "name" t " IS " "nature" " (" "[index range]" ")" delete-char -2 " TOLERANCE " "[string expression]" "\"\"" " ACROSS " "string expression" " THROUGH" ";" vhdl-comment-insert-inline] 7 (#$ . 211180) nil]) #@27 Insert a subprogram body. (defalias 'vhdl-template-subprogram-body #[nil "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-body vhdl-template-procedure-body] 4 (#$ . 211817) nil]) #@34 Insert a subprogram declaration. (defalias 'vhdl-template-subprogram-decl #[nil "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-decl vhdl-template-procedure-decl] 4 (#$ . 212085) nil]) #@31 Insert a subtype declaration. (defalias 'vhdl-template-subtype #[nil "`\301\302!\210\303\304\305\306`%\205*�\301\307!\210\303\310\311\"\210\303\312\305\306#\204%�\313\314!\210\315c\210\316 )\207" [start vhdl-insert-keyword "SUBTYPE " vhdl-template-field "name" nil t " IS " "type" " " "[RANGE value range | ( index range )]" delete-char -1 ";" vhdl-comment-insert-inline] 6 (#$ . 212360) nil]) #@32 Insert a terminal declaration. (defalias 'vhdl-template-terminal #[nil "`\301\302!\210\303\304\305\306`%\205�\307c\210\303\310!\210\311c\210\312 )\207" [start vhdl-insert-keyword "TERMINAL " vhdl-template-field "names" nil t " : " "nature" ";" vhdl-comment-insert-inline] 6 (#$ . 212762) nil]) #@28 Insert a type declaration. (defalias 'vhdl-template-type #[nil "`\305\211\211\306\307!\210\310\311\305\312 `%\211\205\234�\306\313!\210\310\314\305\312#\206%�\315\226\211\315\232\2037�\316\317!\210\320c\210\202\205�\f\321\232\203I�\322\323!\210\324\325\312\"\210\202\205�\f\326\232\203_�\327 \322\323!\210\330\325\n\312#\210\202\205�\f\331\232\203p�\332c\210\310\333\320\"\210\202\205�\f\334\232\203\202�\306\335!\210\310\333\320\"\210\202\205�\320c\210 \203\222�\327  b\210\305\210\336 \210\205\233�b),\207" [end-pos mid-pos name start definition nil vhdl-insert-keyword "TYPE " vhdl-template-field "name" t " IS " "[scalar type | ARRAY | RECORD | ACCESS | FILE]" "" backward-delete-char 4 ";" "ARRAY" kill-word -1 vhdl-template-array type "RECORD" point-marker vhdl-template-record "ACCESS" " " "type" "FILE" " OF " vhdl-comment-insert-inline] 7 (#$ . 213065) nil]) #@22 Insert a use clause. (defalias 'vhdl-template-use #[nil "`\305\306\307\310\311 #\210\312\313!\210\212\314 \210\315\316!)\2057�\312\317!\210\320u\210\321\322\306\305 `\323\\%\2057�\324u\210\321\325!\210\326u\f\204B�\307\310\327 #\210\n+\207" [case-fold-search start result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" vhdl-insert-keyword "USE " beginning-of-line looking-at "^\\s-*use\\>" "..ALL;" -6 vhdl-template-field "library name" 6 1 "package name" 5 "_"] 7 (#$ . 213950) nil]) #@32 Insert a variable declaration. (defalias 'vhdl-template-variable #[nil "`\306\307 \310\311\312\313\f#\210\212\314\315\310\306#\205�\316v\210\317\320!?)\204.�\212\316v\210\317\321!)\2034�\322\323!\2027�\322\324! \204B�\311\312\325\f#\210 \210)\326\327\310\306\n`%\205\205�\330c\210\203\\�\326\331\332\306#\210\326\333!\210\203l�\334c\210\335 \202\205�` \336c\210\326\337\310\306#\204� `|\210\334c\210\335 )+\207" [in-arglist case-fold-search start result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t vhdl-in-argument-list-p nil modify-syntax-entry 95 "w" re-search-backward "\\<function\\|procedure\\|process\\|procedural\\|end\\>" -1 looking-at "\\<end\\>" "\\<shared\\>" vhdl-insert-keyword "VARIABLE " "SHARED VARIABLE " "_" vhdl-template-field "names" " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]" position] 6 (#$ . 214486) nil]) #@26 Insert a wait statement. (defalias 'vhdl-template-wait #[nil "\300\301!\210\302\303\304\305#\204�\306\307!\210\310c\207" [vhdl-insert-keyword "WAIT " vhdl-template-field "[ON sensitivity list] [UNTIL condition] [FOR time expression]" nil t delete-char -1 ";"] 4 (#$ . 215397) nil]) #@46 Indent correctly if within a case statement. (defalias 'vhdl-template-when #[nil "`\306\307\307\310\311\312\f#\210i\313 U\2033�\314\315\307\306#\2033�\316\317!\2033�\313 \nb\210\320 \210 \\j\2025�\nb\204A�\310\311\321\f#\210 \210)\322\323!+\207" [margin case-fold-search position result vhdl-mode-syntax-table vhdl-basic-offset t nil modify-syntax-entry 95 "w" current-indentation re-search-forward "\\<end\\>" looking-at "\\s-*\\<case\\>" delete-horizontal-space "_" vhdl-insert-keyword "WHEN " vhdl-underscore-is-part-of-word] 4 (#$ . 215686) nil]) #@22 Insert a while loop. (defalias 'vhdl-template-while-loop #[nil "\306 `\307 \310=\204�\311\312!\210\202/�\311\313!\210 b\210\314\315\307\316#\211\204)�\317\320!\210\321v\210\321u\210\f\2036�\322c\210\314\323\307\316 `%\205g�\f\203G�\324c\210\311\325!\210j\210\311\326!\210\n\203]�\327\n\330Q\202^�\330c\210\331y\210 \\j+\207" [margin start label vhdl-optional-labels vhdl-conditions-in-parenthesis vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "WHILE " ": WHILE " vhdl-template-field "[label]" t delete-char 2 1 "(" "condition" ")" " LOOP\n\n" "END LOOP" " " ";" -1] 7 (#$ . 216252) nil]) #@60 Insert a with statement (i.e. selected signal assignment). (defalias 'vhdl-template-with #[nil "\304\305\306\307\310\n#\210\212\311\312!\210\313\314!\315\232)\203�\316 \202 �\317\320! \204+�\306\307\321\n#\210 *\207" [case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-backward "\\(\\<limit\\>\\|;\\)" match-string 1 ";" vhdl-template-selected-signal-asst vhdl-insert-keyword "WITH " "_"] 4 (#$ . 216873) nil]) #@56 Insert a wait statement for rising/falling clock edge. (defalias 'vhdl-template-clocked-wait #[nil "`\306\307\310!\210\n\311\232\204�\nc\210\n\206�\312\313\306\314 `%\211\205F�\315c\210\307\316!\210c\210\317 \2034�\f\2025� \320\261\210\321 \203B�\322\202C�\323\324P!*\207" [clock start vhdl-clock-name vhdl-clock-rising-edge vhdl-one-string vhdl-zero-string nil vhdl-insert-keyword "WAIT UNTIL " "" vhdl-template-field "clock name" t "'event" " AND " " = " ";" vhdl-comment-insert-inline "rising" "falling" " clock edge"] 6 (#$ . 217365) nil]) #@57 Insert a template for the body of a sequential process. (defalias 'vhdl-template-seq-process #[(clock reset) "\306 \307\310\311!\210\n\312=\203F� \313\f\203� \202�%\261\210\310\314!\210\315\316\f\203,�\317\202-�\320\321Q!\210\322c\210 &\\j\210`\322c\210 j\210\310\323!\210'\324=\203a�(\203V�\325\202W�\326\327)\321\261\210\202|�)\330\261\210\310\331!\210)\313(\203w� \202y�%\261\210\310\314!\210\315(\203\212�\325\202\213�\326\332P!\210\322c\210 &\\j\210\n\333=\203\310\311!\210*\334\232\204\262�*c\210*\206\271�\335\336!\206\271�\337\313\f\203\303� \202\305�%\261\210\310\314!\210\315\340\f\203\326�\317\202\327�\320\321Q!\210\322c\210 &\211\\\341\\\\j\210`\322c\210 &\\j\210\310\342!\210\322c\210 &\211\\\341\\\\j\210\322c\210 &\\j\210\310\343!\210\n\344=\203`\322c\210 j\210\310\343!\210b\210 *\207" [position margin vhdl-reset-kind reset vhdl-reset-active-high vhdl-one-string current-indentation nil vhdl-insert-keyword "IF " async " = " " THEN" vhdl-comment-insert-inline "asynchronous reset (active " "high" "low" ")" "\n" "ELSIF " function "rising" "falling" "_edge(" "'event" " AND " " clock edge" sync "" vhdl-template-field "reset name" "<reset>" "synchronous reset (active " 0 "ELSE" "END IF;" none vhdl-zero-string vhdl-basic-offset vhdl-clock-edge-condition vhdl-clock-rising-edge clock vhdl-reset-name] 4 (#$ . 217922)]) #@101 Insert specification of a standard package. Include a library specification, if not already there. (defalias 'vhdl-template-standard-package #[(library package) "\306 \307\212\310\311\312\313 #\210o?\205�\314\315\f\316Q\310\307# \204&�\311\312\317 #\210\n\210*\320\321!\2038�\322\323\320\321!\"\204D�\324\325!\210\f\326\261\210 j\210\324\327!\210\f\330\261\210\324\331!*\207" [case-fold-search margin result vhdl-mode-syntax-table library vhdl-underscore-is-part-of-word current-indentation t nil modify-syntax-entry 95 "w" re-search-backward "^\\s-*\\(library\\s-+\\(\\(\\w\\|\\s_\\)+,\\s-+\\)*" "\\|end\\)\\>" "_" match-string 1 string-match "library" vhdl-insert-keyword "LIBRARY " ";\n" "USE " "." ".ALL;" package] 4 (#$ . 219302)]) #@49 Insert specification of `math_complex' package. (defalias 'vhdl-template-package-math-complex #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_complex"] 3 (#$ . 220055) nil]) #@46 Insert specification of `math_real' package. (defalias 'vhdl-template-package-math-real #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_real"] 3 (#$ . 220259) nil]) #@48 Insert specification of `numeric_bit' package. (defalias 'vhdl-template-package-numeric-bit #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_bit"] 3 (#$ . 220454) nil]) #@48 Insert specification of `numeric_std' package. (defalias 'vhdl-template-package-numeric-std #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_std"] 3 (#$ . 220655) nil]) #@51 Insert specification of `std_logic_1164' package. (defalias 'vhdl-template-package-std-logic-1164 #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_1164"] 3 (#$ . 220856) nil]) #@52 Insert specification of `std_logic_arith' package. (defalias 'vhdl-template-package-std-logic-arith #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_arith"] 3 (#$ . 221066) nil]) #@51 Insert specification of `std_logic_misc' package. (defalias 'vhdl-template-package-std-logic-misc #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_misc"] 3 (#$ . 221279) nil]) #@53 Insert specification of `std_logic_signed' package. (defalias 'vhdl-template-package-std-logic-signed #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_signed"] 3 (#$ . 221489) nil]) #@53 Insert specification of `std_logic_textio' package. (defalias 'vhdl-template-package-std-logic-textio #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_textio"] 3 (#$ . 221705) nil]) #@55 Insert specification of `std_logic_unsigned' package. (defalias 'vhdl-template-package-std-logic-unsigned #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_unsigned"] 3 (#$ . 221921) nil]) #@43 Insert specification of `textio' package. (defalias 'vhdl-template-package-textio #[nil "\300\301\302\"\207" [vhdl-template-standard-package "std" "textio"] 3 (#$ . 222143) nil]) #@19 Insert directive. (defalias 'vhdl-template-directive #[(directive) "\301 iU\204 �\302 \210\303c\210\304\261\207" [directive current-indentation delete-horizontal-space " " "-- pragma "] 2 (#$ . 222328)]) #@34 Insert directive 'translate_on'. (defalias 'vhdl-template-directive-translate-on #[nil "\300\301!\207" [vhdl-template-directive "translate_on"] 2 (#$ . 222541) nil]) #@35 Insert directive 'translate_off'. (defalias 'vhdl-template-directive-translate-off #[nil "\300\301!\207" [vhdl-template-directive "translate_off"] 2 (#$ . 222713) nil]) #@34 Insert directive 'synthesis_on'. (defalias 'vhdl-template-directive-synthesis-on #[nil "\300\301!\207" [vhdl-template-directive "synthesis_on"] 2 (#$ . 222888) nil]) #@35 Insert directive 'synthesis_off'. (defalias 'vhdl-template-directive-synthesis-off #[nil "\300\301!\207" [vhdl-template-directive "synthesis_off"] 2 (#$ . 223060) nil]) #@18 Indent comments. (defalias 'vhdl-comment-indent #[nil "`\303y\210\304\305\306#\203�i\307Z\202�b\210\310\311x\210 iT]b\210\n*\207" [position comment-column col -1 re-search-forward "--" t 2 " " nil] 4 (#$ . 223235)]) #@153 Start a comment at the end of the line. If on line with code, indent at least `comment-column'. If starting after end-comment-column, start a new line. (defalias 'vhdl-comment-insert #[nil "iV\203 �\306 \210\307\310!\204� \204K�\311\204K�\311h\312U\203'�\313\314!\210\202�i\315 \210n\2039�\nj\210\316c\210\202B�\317c\210 j\210\316c\210 ?\205I�\320c)\207\311\211h\312U\203\\�\313\321!\210\202O�\322 \211\323U\203w�\316c\210\321u\210\324y\210\325\326!\210\327\202\\�\f\204~�\316c\210\330 !C\211*\207" [end-comment-column unread-command-events margin comment-column code next-input newline-and-indent looking-at "\\s-*$" nil 45 delete-char -1 delete-horizontal-space "--" " " " " -2 read-char 13 1 message "Enter CR if commenting out a line of code." t vhdl-character-to-event] 2 (#$ . 223466) nil]) #@70 Add 2 comment lines at the current indent, making a display comment. (defalias 'vhdl-comment-display #[(&optional line-exists) "\302  \204\n�\303 \210\304c\210j\210\304c\210j\210\303 \210\305\210\306c)\207" [margin line-exists current-indentation vhdl-comment-display-line "\n" 0 "-- "] 1 (#$ . 224281) nil]) #@30 Displays one line of dashes. (defalias 'vhdl-comment-display-line #[nil "h\303U\203 �\304\305!\210\202��i Z\306\303\n\"*\207" [col end-comment-column len 45 delete-char -2 insert-char] 3 (#$ . 224600) nil]) #@46 Append empty inline comment to current line. (defalias 'vhdl-comment-append-inline #[nil "\301\210\302 \210\303c\210j\210\304c\207" [comment-column nil delete-horizontal-space " " "-- "] 1 (#$ . 224816) nil]) #@24 Insert inline comment. (defalias 'vhdl-comment-insert-inline #[(&optional string always-insert) "\203\f� \204�\n\204�?\205O� \205O�`\306c\210 j\210\307c\210\203*�c\210\2022�\310\311\312\313#\203K�iV\205N�\314 \315\307!\210\316c\210 j\210\fb\202N�\f`|)\207" [string vhdl-self-insert-comments always-insert vhdl-prompt-for-comments position comment-column " " "-- " vhdl-template-field "[comment]" nil t point-marker re-search-backward "\n" end-comment-column] 4 (#$ . 225034)]) #@32 Insert comment for code block. (defalias 'vhdl-comment-block #[nil "\205_�\306 \307\310\311\312\313\f#\210\314\315\310\307#\205M�\314\316\310\307#\205M�\310\317 \210i\320\210o\2038�\321c\210\322y\210\202;�\321c\210 j\210\323c\210\324\325\310\307#?\205L�\326 )\204Y�\311\312\327\f#\210 \210)\nb*\207" [vhdl-prompt-for-comments case-fold-search final-pos result vhdl-mode-syntax-table margin point-marker t nil modify-syntax-entry 95 "w" re-search-backward "^\\s-*begin\\>" "\\<\\(architecture\\|block\\|function\\|procedure\\|process\\|procedural\\)\\>" back-to-indentation 0 "\n" -1 "-- purpose: " vhdl-template-field "[description]" vhdl-line-kill-entire "_" vhdl-underscore-is-part-of-word] 4 (#$ . 225528)]) #@63 Comment out region if not commented out, uncomment otherwise. (defalias 'vhdl-comment-uncomment-region #[(beg end &optional arg) "\212Sb\210\303\210\304  b\210\305 \210`\306\n!\203!�\307 \310#\202%�\307 \")\207" [end beg comment-start nil point-marker beginning-of-line looking-at comment-region -2] 4 (#$ . 226255) "r\nP"]) #@61 Comment out line if not commented out, uncomment otherwise. (defalias 'vhdl-comment-uncomment-line #[(&optional arg) "\212\302 \210` \206 �\303y\210\304`\"*\207" [position arg beginning-of-line 1 vhdl-comment-uncomment-region] 3 (#$ . 226592) "p"]) #@26 Kill comments in region. (defalias 'vhdl-comment-kill-region #[(beg end) "\212b\210\302  b\210\303 \210`W\205)�\304\305!\203\"�\306\224\306\225|\210\202 �\303\307!\210\202 �)\207" [end beg point-marker beginning-of-line looking-at "^\\(\\s-*--.*\n\\)" 1 2] 2 (#$ . 226849) "r"]) #@33 Kill inline comments in region. (defalias 'vhdl-comment-kill-inline-region #[(beg end) "\212b\210\302  b\210\303 \210`W\205&�\304\305!\203�\306\224\306\225|\210\303\307!\210\202 �)\207" [end beg point-marker beginning-of-line looking-at "^.*[^ \n-]+\\(\\s-*--.*\\)$" 1 2] 2 (#$ . 227137) "r"]) #@91 Insert a begin ... end pair with optional name after the end. Point is left between them. (defalias 'vhdl-template-begin-end #[(construct name margin &optional empty-lines) "\306\307c\210 \204�\n\310=\203�\307c\210 j\210\311\312!\210\f\204!� \203=�\203=�\313c\210\f\2034�\314c\210\311\f!\210 \203=�\314 \261\210\307c\210 \204J�\n\310=\203M�\307c\210 \\j\210`\307c\210 \204b�\n\310=\203e�\307c\210 j\210\311\315!\210\f\203w�\314c\210\311\f!\210 \203\201�\314 P\202\202�\316\317\261\210b)\207" [position empty-lines vhdl-insert-empty-lines margin construct name nil "\n" all vhdl-insert-keyword "BEGIN" " --" " " "END" "" ";" vhdl-self-insert-comments vhdl-basic-offset] 2 (#$ . 227442)]) #@55 Read from user a procedure or function argument list. (defalias 'vhdl-template-argument-list #[(&optional is-function) "\306c\210i``\307\211\211\204 �\310 \\\311c\210 j\210\312\313 ?\205)�\314\315Q\316\317#\312\320\307\317#\203�\317\321c\210 \204Y� \203S� \226\322\232\203S�\323\324!\210\202Y�\312\325\316\317#\210\312\326!\210`\327c\210\330 \210`\311c\210 j\210\312\313 ?\205v�\314\315Q\316\317#\202/� `|\210\203\212�b\210\n\203\227�\331\332!\210\333c\202\232�\334\335!.\207" [semicolon-pos interface not-empty end-pos start margin " (" nil current-indentation "\n" vhdl-template-field "[CONSTANT | SIGNAL" " | VARIABLE" "]" " " t "[names]" " : " "CONSTANT" vhdl-insert-keyword "IN " "[IN | OUT | INOUT]" "type" ";" vhdl-comment-insert-inline delete-char 1 ")" backward-delete-char 2 vhdl-argument-list-indent vhdl-basic-offset is-function] 6 (#$ . 228147)]) #@46 Read from user a generic spec argument list. (defalias 'vhdl-template-generic-list #[(optional &optional no-value) "\306`\307\310!\210i\n\204!�`\311 \210i\f\\ b\210\312c\210 j\210)\313 \205'�\314\315 \205.�\316 \2053�\317R\306 #\211!\204]� \203T�\320 \210\321\210\n?\205\315�\320 \210\321\202\315�\322`\"\210\306\202\315�\323c\210\306\211\"#!\203\261�\313\324!\210 \203}�`#\325c\210\202\222�\326c\210\313\327\306\330#\204\214�\331\332!\210`#\325c\210\333 \210`\"\312c\210 j\210\313\334 \205\246�\316\317Q\323\330#\211!\204k�\"`|\210#b\210\335c\210\306\210$\203\313�\336`\337#\210*\330+\207" [start margin vhdl-argument-list-indent position vhdl-basic-offset optional nil vhdl-insert-keyword "GENERIC (" back-to-indentation "\n" vhdl-template-field "[" "name" "s" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "type" ";" " := " "[value]" t delete-char -4 vhdl-comment-insert-inline "[name" ")" vhdl-align-noindent-region 1 no-value vhdl-generics end-pos semicolon-pos vhdl-auto-align] 6 (#$ . 229036)]) #@43 Read from user a port spec argument list. (defalias 'vhdl-template-port-list #[(optional) "`\306\211\211\307\310!\210i\f\204&�`\311 \210i$\\ b\210\312c\210\nj\210)\313%\313&@=\206<�%&\211'A@)>)\203F�\314\315\316\317#\314(\205M�\320\321(\205T�\322Q\306(#\211\204�(\203v�\323 \210\324\210\f?\205\323 \210\324\202\325 `\"\210\306\202\326c\210\306\211)* \203\373�\203\227�\226\327\232\203\237�\314\330\316\"\210\202\254�\226\331\232\203\254�\314\332\316\317#\210\314\203\274�\226\333\232\203\274�\334\202\275�\335!\210`*\336c\210\337 \210`)\312c\210\nj\210\313%\313&@=\206\347�%&\211'A@)>)\203\361�\314\315\316\317#\314\340\326\317#\211\204\214�)`|\210*b\210\341c\210\306\210+\203\342 )\343#\210*\317,\207" [object vhdl-ports margin start vhdl-argument-list-indent position nil vhdl-insert-keyword "PORT (" back-to-indentation "\n" ams vhdl-template-field "[SIGNAL | TERMINAL | QUANTITY]" " " t "[" "names" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "SIGNAL" "IN | OUT | INOUT" "QUANTITY" "[IN | OUT]" "TERMINAL" "nature" "type" ";" vhdl-comment-insert-inline "[names]" ")" vhdl-align-noindent-region 1 vhdl-basic-offset standard vhdl-standard x optional end-pos semicolon-pos vhdl-auto-align] 5 (#$ . 230075)]) #@36 Insert body for generate template. (defalias 'vhdl-template-generate-body #[(margin label) "\306\307!\210\310\310 @=\206� \211A@)>)\204�\311\312 \f#\207\313c\210\fj\210\306\314!\210 \315\261\210\316\210\f \\j\207" [standard vhdl-standard x label margin vhdl-basic-offset vhdl-insert-keyword " GENERATE" 87 vhdl-template-begin-end "GENERATE" "\n\n" "END GENERATE " ";" 0] 4 (#$ . 231350)]) #@36 Insert date in appropriate format. (defalias 'vhdl-template-insert-date #[nil "\301=\203 �\302\303\304\"\202+�\305=\203�\302\306\304\"\202+�\307=\203'�\302\310\304\"\202+�\302\304\"c\207" [vhdl-date-format american format-time-string "%m/%d/%Y" nil european "%d.%m.%Y" scientific "%Y/%m/%d"] 3 (#$ . 231752) nil]) #@118 Expand abbreviations and self-insert space(s), do indent-new-comment-line if in comment and past end-comment-column. (defalias 'vhdl-electric-space #[(count) "`\212\306 \210\307\310\311#*\2032�\312 !\210i\n\313\\Y\203'�\314v\210\315 \210\316v\210\316u\207i\nY\2030�\315 \207\317\207h\320Y\203>�h\321X\204J�h\322Y\203j�h\323X\203j�\317\324\325\326\f#\210\311\327 )\204c�\324\325\330\f#\210 \210)\312 !\207\312 !\207" [position count end-comment-column result vhdl-mode-syntax-table case-fold-search beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" t self-insert-command 2 -1 indent-new-comment-line 1 nil 97 122 65 90 modify-syntax-entry 95 "w" expand-abbrev "_" vhdl-underscore-is-part-of-word] 4 (#$ . 232078) "p"]) #@368 Prompt for string and insert it in buffer with optional FOLLOW-STRING. If OPTIONAL is nil, the prompt is left if an empty string is inserted. If an empty string is inserted, return nil and call `vhdl-template-undo' for the region between BEGIN and END. IS-STRING indicates whether a string with double-quotes is to be inserted. DEFAULT specifies a default string. (defalias 'vhdl-template-field #[(prompt &optional follow-string optional begin end is-string default) "`\306\307\n\310\261\210\306\311\312\217\211\313\232\203� \203� `|\210\313\232\2038� \2038�\f\2038� \2038�\314\f \"\210\315\316!\210\313\232\204J�c\210\317 `$\210\313\232\203T� \204\\�\206Z�\313c\210\313\232?\205d�*\207" [string position prompt optional begin end nil "<" ">" (byte-code "\304\305P \203\f�\306\202 �\n #\207" [prompt is-string default vhdl-minibuffer-local-map read-from-minibuffer ": " ("\"\"" . 2)] 4) ((quit (byte-code "\203� \203�\n\203�\303 \210\304\207\305 \207" [optional begin end beep "" keyboard-quit] 1))) "" vhdl-template-undo message "Template aborted" vhdl-fix-case-region-1 vhdl-upper-case-keywords vhdl-keywords-regexp follow-string] 6 (#$ . 232831)]) #@33 Query a decision from the user. (defalias 'vhdl-decision-query #[(string prompt &optional optional) "` \203\f�\305 \306P!\210\307\n!\210\310 `|\210\f\203.� \311=\203.�\306c\210\312 \210\313\314\315\"\202/� *\207" [start string prompt char optional vhdl-insert-keyword " " message read-char 13 unexpand-abbrev throw abort "Template aborted"] 3 (#$ . 234014)]) #@33 Insert KEYWORD and adjust case. (defalias 'vhdl-insert-keyword #[(keyword) "\203 � \226\202 � \227c\207" [vhdl-upper-case-keywords keyword] 1 (#$ . 234382)]) #@25 Adjust case of KEYWORD. (defalias 'vhdl-case-keyword #[(keyword) "\203� \226\207 \227\207" [vhdl-upper-case-keywords keyword] 1 (#$ . 234547)]) #@37 Adjust case or following NUM words. (defalias 'vhdl-case-word #[(num) "\203�\302 !\207\303 !\207" [vhdl-upper-case-keywords num upcase-word downcase-word] 2 (#$ . 234699)]) #@237 If preceeding character is part of a word or a paren then hippie-expand, else if right of non whitespace on line then tab-to-tab-stop, else indent line in proper way for current major mode (used for word completion in VHDL minibuffer). (defalias 'vhdl-minibuffer-tab #[(&optional prefix-arg) "hz\305U\203�?\306\307 !*\207h\310U\204�h\311U\203'�?\306\312 !*\207i\313 V\2031�\314 \207\f\315=\203;�\316 !\207 \203C�\f !\207\f \207" [vhdl-word-completion-case-sensitive case-replace case-fold-search prefix-arg indent-line-function 119 nil vhdl-expand-abbrev 40 41 vhdl-expand-paren current-indentation tab-to-tab-stop indent-to-left-margin insert-tab] 2 (#$ . 234881) "P"]) #@55 Search for left out template prompts and query again. (defalias 'vhdl-template-search-prompt #[nil "\306\307\310\311\312\n#\210\313\314 \315Q\307\306#\204 �\316\314 \315Q\307\306#\205,�\317\320!\321\322!\210\323\f!) \2047�\310\311\324\n#\210 *\207" [case-fold-search result vhdl-mode-syntax-table vhdl-template-prompt-syntax string vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" re-search-forward "<\\(" "\\)>" re-search-backward match-string 1 replace-match "" vhdl-template-field "_"] 4 (#$ . 235566) nil]) #@71 Undo aborted template by deleting region and unexpanding the keyword. (defalias 'vhdl-template-undo #[(begin end) "\203� b\210\303c\210\n |\210\304 \207\n |\207" [vhdl-template-invoked-by-hook end begin " " unexpand-abbrev] 2 (#$ . 236103)]) #@68 Insert STRING or file contents if STRING is an existing file name. (defalias 'vhdl-insert-string-or-file #[(string) "\302\232?\205�\303!\203�\304!\211A@)u\207c\207" [string x "" file-exists-p insert-file-contents] 3 (#$ . 236353)]) #@53 Check if point is within sequential statement part. (defalias 'vhdl-sequential-statement-p #[nil "\212\305`\306\307\310\311 #\210\312\306!\210\313\314\306\305#\203�\315\316!\204�\317 \205<�\315\320!\226\321\232\205<�\313\322\306\305#\205<�\315\323!\226\324\232?\f\204G�\307\310\325 #\210\n,\207" [start case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" set-match-data re-search-backward "^\\s-*\\(begin\\|end\\(\\s-*\\(case\\|if\\|loop\\)\\)?\\)\\>" match-string 2 match-data 1 "BEGIN" "^\\s-*\\(\\w+\\s-*:\\s-*\\)?\\(\\w+\\s-+\\)?\\(function\\|procedure\\|process\\|procedural\\|end\\)\\>" 3 "END" "_"] 4 (#$ . 236598)]) #@35 Check if within an argument list. (defalias 'vhdl-in-argument-list-p #[nil "\212\304\305\306\307\310\n#\210\311\312\313\314\315 @@\"\"\206�\316 \210\317\320! \204)�\306\307\321\n#\210 +\207" [case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word t nil modify-syntax-entry 95 "w" string-match "arglist" format "%s" vhdl-get-syntactic-context beginning-of-line looking-at "^\\s-*\\(generic\\|port\\|\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\>\\s-*\\(\\w+\\s-*\\)?(" "_"] 5 (#$ . 237294)]) #@115 Do function, if syntax says abbrev is a keyword, invoked by hooked abbrev, but not if inside a comment or quote). (defalias 'vhdl-hooked-abbrev #[(func) "`\212\306 \210\307\310\311#*\2042�`\212\306 \210\307\312\311#*=\2042�\212\313v\210\314\315!\205.�\314\316!?)\203<�\317c\210\320 \210\321\313!\207 \204Q�\317c\210\320 \210\313v\210\322\323!\210\321\323!\207\n\313\311\324\325\215\211;\203f�\326!\210) \327U\203p�`\330\331\"\203�\332\321\313\"\202\206�\333\334!C\211 +\207" [position vhdl-electric-mode last-command-char vhdl-template-invoked-by-hook abbrev-mode invoke-char beginning-of-line re-search-forward "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" t "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*\"[^\"]*" -1 looking-at "\\<end\\>" "\\<end;" " " unexpand-abbrev delete-char vhdl-case-word 1 abort (funcall func) message 45 string-match "XEmacs" enqueue-eval-event vhdl-character-to-event 127 caught abbrev-start-location emacs-version unread-command-events] 6 (#$ . 237833)]) (defalias 'vhdl-template-alias-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-alias] 2]) (defalias 'vhdl-template-architecture-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-architecture] 2]) (defalias 'vhdl-template-assert-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-assert] 2]) (defalias 'vhdl-template-attribute-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-attribute] 2]) (defalias 'vhdl-template-block-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-block] 2]) (defalias 'vhdl-template-break-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-break] 2]) (defalias 'vhdl-template-case-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-case] 2]) (defalias 'vhdl-template-component-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-component] 2]) (defalias 'vhdl-template-instance-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-instance] 2]) (defalias 'vhdl-template-conditional-signal-asst-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-conditional-signal-asst] 2]) (defalias 'vhdl-template-configuration-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-configuration] 2]) (defalias 'vhdl-template-constant-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-constant] 2]) (defalias 'vhdl-template-disconnect-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-disconnect] 2]) (defalias 'vhdl-template-display-comment-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-comment-display] 2]) (defalias 'vhdl-template-else-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-else] 2]) (defalias 'vhdl-template-elsif-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-elsif] 2]) (defalias 'vhdl-template-entity-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-entity] 2]) (defalias 'vhdl-template-exit-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-exit] 2]) (defalias 'vhdl-template-file-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-file] 2]) (defalias 'vhdl-template-for-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-for] 2]) (defalias 'vhdl-template-function-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-function] 2]) (defalias 'vhdl-template-generic-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-generic] 2]) (defalias 'vhdl-template-group-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-group] 2]) (defalias 'vhdl-template-library-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-library] 2]) (defalias 'vhdl-template-limit-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-limit] 2]) (defalias 'vhdl-template-if-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-if] 2]) (defalias 'vhdl-template-bare-loop-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-bare-loop] 2]) (defalias 'vhdl-template-map-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-map] 2]) (defalias 'vhdl-template-nature-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nature] 2]) (defalias 'vhdl-template-next-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-next] 2]) (defalias 'vhdl-template-package-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-package] 2]) (defalias 'vhdl-template-port-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-port] 2]) (defalias 'vhdl-template-procedural-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedural] 2]) (defalias 'vhdl-template-procedure-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedure] 2]) (defalias 'vhdl-template-process-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-process] 2]) (defalias 'vhdl-template-quantity-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-quantity] 2]) (defalias 'vhdl-template-report-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-report] 2]) (defalias 'vhdl-template-return-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-return] 2]) (defalias 'vhdl-template-selected-signal-asst-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-selected-signal-asst] 2]) (defalias 'vhdl-template-signal-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-signal] 2]) (defalias 'vhdl-template-subnature-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subnature] 2]) (defalias 'vhdl-template-subtype-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subtype] 2]) (defalias 'vhdl-template-terminal-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-terminal] 2]) (defalias 'vhdl-template-type-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-type] 2]) (defalias 'vhdl-template-use-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-use] 2]) (defalias 'vhdl-template-variable-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-variable] 2]) (defalias 'vhdl-template-wait-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-wait] 2]) (defalias 'vhdl-template-when-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-when] 2]) (defalias 'vhdl-template-while-loop-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-while-loop] 2]) (defalias 'vhdl-template-with-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-with] 2]) (defalias 'vhdl-template-and-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-and] 2]) (defalias 'vhdl-template-or-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-or] 2]) (defalias 'vhdl-template-nand-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nand] 2]) (defalias 'vhdl-template-nor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nor] 2]) (defalias 'vhdl-template-xor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xor] 2]) (defalias 'vhdl-template-xnor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xnor] 2]) (defalias 'vhdl-template-not-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-not] 2]) (defalias 'vhdl-template-default-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default] 2]) (defalias 'vhdl-template-default-indent-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default-indent] 2]) #@51 Insert the built-in construct template with NAME. (defalias 'vhdl-template-insert-construct #[(name) "\302\303 \"A@!\207" [name vhdl-template-construct-alist vhdl-template-insert-fun assoc] 4 (#$ . 245097) (list (let ((completion-ignore-case t)) (completing-read "Construct name: " vhdl-template-construct-alist nil t)))]) #@49 Insert the built-in package template with NAME. (defalias 'vhdl-template-insert-package #[(name) "\302\303 \"A@!\207" [name vhdl-template-package-alist vhdl-template-insert-fun assoc] 4 (#$ . 245427) (list (let ((completion-ignore-case t)) (completing-read "Package name: " vhdl-template-package-alist nil t)))]) #@51 Insert the built-in directive template with NAME. (defalias 'vhdl-template-insert-directive #[(name) "\302\303 \"A@!\207" [name vhdl-template-directive-alist vhdl-template-insert-fun assoc] 4 (#$ . 245747) (list (let ((completion-ignore-case t)) (completing-read "Directive name: " vhdl-template-directive-alist nil t)))]) #@41 Call FUN to insert a built-in template. (defalias 'vhdl-template-insert-fun #[(fun) "\301\302\215\211;\205\f�\303!)\207" [caught abort (byte-code "\205� \207" [fun] 1) message] 3 (#$ . 246077)]) #@45 Insert the user model with name MODEL-NAME. (defalias 'vhdl-model-insert #[(model-name) "\306 \210\307 \310 \311\312\211\211\211\211$%\312&\313\314\315'#\210\316()\"\211\205\356�\317 \210\320 \210%b\210\321\fA@!\210\307 %b\210\317 \210`W\203_�\322\323!\204X�\324\325$\"\210\317\326!\210\202F�%b\210*\327\232\204z�\330\331\311#\203z�\332*!\210\202j�%b\210+\327\232\204\225�\330\333\311#\203\225�\332+!\210\202\205�%b\210\330\334,\335Q\311#\203\332�\336\337!\340\232\204\231�\337\224\336\337!\332\327!\210\341\n\312\311#\330\334\n\335Q\311#\203\324�\332 \206\317�\327!\210\202\276� b\210\202\231�%b\210\330\342\311#\203\354�\332\327!\202\356�b&-\204\374�\313\314\343'#\210&. \207" [end string prompt position model case-fold-search vhdl-indent-line point-marker current-indentation t nil modify-syntax-entry 95 "w" assoc beginning-of-line delete-horizontal-space vhdl-insert-string-or-file looking-at "^$" insert-char 32 2 "" re-search-forward "<clock>" replace-match "<reset>" "<\\(" "\\)>" match-string 1 "cursor" vhdl-template-field "<cursor>" "_" margin start result vhdl-mode-syntax-table model-name vhdl-model-alist vhdl-clock-name vhdl-reset-name vhdl-template-prompt-syntax vhdl-underscore-is-part-of-word] 8 (#$ . 246283) (let ((completion-ignore-case t)) (list (completing-read "Model name: " vhdl-model-alist)))]) #@49 Define help and hook functions for user models. (defalias 'vhdl-model-defun #[nil "\304\211\211\205G� @@\305\306\307\310\n\"\304\311\n\312Q\313\314\nD\257!\210\315 @8\211\316\232\204?�\305\306\307\310\n\317#\304\320\321\307\310\n\"DDF!\210 A\211\204\n�\304+\207" [vhdl-model-alist model-keyword model-name model-alist nil eval defun vhdl-function-name "vhdl-model" "Insert model for \"" "\"." (interactive) vhdl-model-insert 3 "" "hook" vhdl-hooked-abbrev quote] 10 (#$ . 247652)]) (vhdl-model-defun) #@40 Variable to hold last PORT map parsed. (defvar vhdl-port-list nil (#$ . 248167)) #@131 Check that the text following point matches the regexp in STRING. END is the point beyond which matching/searching should not go. (defalias 'vhdl-parse-string #[(string &optional optional) "\302!\203\f�\303\304\305#\207 \204�\306\307\310\311\312 \"\"\210\304\207" [string optional looking-at re-search-forward nil t throw parse format "Syntax error near line %s" vhdl-current-line] 5 (#$ . 248255)]) #@63 Replace STRING from car of REGEXP-CONS to cdr of REGEXP-CONS. (defalias 'vhdl-replace-string #[(regexp-cons string) "\305\306\307\310 #\210\311\n@ \"\203�\312\nA\313\305 $\202� \f\204&�\306\307\314 #\210)\207" [result vhdl-mode-syntax-table regexp-cons string vhdl-underscore-is-part-of-word nil modify-syntax-entry 95 "w" string-match replace-match t "_"] 5 (#$ . 248664)]) #@66 Flatten port list so that only one generic/port exists per line. (defalias 'vhdl-port-flatten #[nil "\204�\306\307!\207\310\311!\210@CA\312\211\211\211\211  \203c� @\312 \203S� @\211@\211\203L� @C AB\313\f\nC\" A\211\2048� A\211\204.� A \313\fC\"\202�\310\314!.\207" [vhdl-port-list names new-port old-port new-port-list old-port-list error "No port read" message "Flattening port..." nil append "Flattening port...done" old-vhdl-port-list new-vhdl-port-list] 8 (#$ . 249050) nil]) #@75 Get generic and port information from an entity or component declaration. (defalias 'vhdl-port-copy #[nil "\306\307!\210\212\310\311\211\211\211\211\211\211\211\211\211\211\311\312\313\314#\210\315\316\215\211\204A�\312\313\317#\210\210)\203Q�\320!\202]�E\306\321!. \207" [comment init type direct names object message "Reading port..." t nil modify-syntax-entry 95 "w" parse (byte-code "\306\307\310\311#\203�\312\313!\314\232\203�\315\316\317\"\210\313v\210\320\321!\210\312\313!\322 \210\320\323\311\"\203\322 \210\324\325! \204\320\326!\210\312\313!C\320\327\311\"\203P�\330\n\312\313!C\"\202>�\320\331!\210\312\313!\310\324\332!\203v� `\333 \210`{\320\334\311\"\205q�\312\313!Q\202Z� \203\215�\335\336 \"\203\215� \337\224\310O \340\313\224O\335\341 \"\210 \340\313\225O\310\320\342\311\"\203\305�\320\343!\210\312\313!\324\332!\203\305� `\333 \210`{\320\343\311\"\205\300�\312\313!Q\202\251� \203\337�\335\336 \"\203\337� \337\224\310O \340\313\224O\322 \210\344\310w\210\f\204\362�\320\345\311\"\205\361�\312\313!\322 \210\320\325\311\"\320\346!\210\f\204 \320\345\311\"\205\f\312\313!\322 \210\330,\n \fFC\",\2021�\320\347\311\"\203\335\322 \210\324\325! \204\335\320\350\311\"\205;\312\313!-\320\326!\210\312\313!C\320\327\311\"\203X\330\n\312\313!C\"\202F\320\351!\210\320\352\311\"\205f\312\313!.\320\353!\210\312\313!\310\324\332!\203\216 `\333 \210`{\320\343\311\"\205\211\312\313!Q\202r\335\336 \"\203\241 \337\224\310O \340\313\224O\335\341 \"\210 \340\313\225O\322 \210\320\325\311\"\320\346!\210\f\204\307\320\345\311\"\205\306\312\313!\322 \210\330/\n-. \f\257C\"/\202-\310\207" [name end-of-list names type comment init re-search-backward "^\\s-*\\(component\\|entity\\|end\\)\\>" nil t match-string 1 "end" throw parse "Not within entity or component declaration" vhdl-parse-string "\\s-*\\(\\w+\\)\\s-*\\(is\\)?\\s-*$" vhdl-forward-syntactic-ws "generic[ \n]*(" looking-at ")" "\\(\\w+\\)[ \n]*" ",[ \n]*\\(\\w+\\)[ \n]*" append ":[ \n]*\\([^():;\n]+\\)" "(" forward-sexp "\\([^():;\n]*\\)" string-match "\\(\\s-*--\\s-*\\)\\(.*\\)" 2 0 "\\(\\(\\s-*\\S-+\\)+\\)\\s-*" ":=[ \n]*" "\\([^();\n]*\\)" " " "--\\s-*\\([^\n]*\\)" ";\\s-*" "port[ \n]*(" "\\(signal\\|quantity\\|terminal\\)[ \n]*" ":[ \n]*" "\\(IN\\|OUT\\|INOUT\\)[ \n]+" "\\([^();\n]+\\)" generics object direct ports] 7) "_" error "Reading port...done" ports generics name end-of-list parse-error case-fold-search result vhdl-mode-syntax-table vhdl-underscore-is-part-of-word vhdl-port-list] 12 (#$ . 249571) nil]) #@25 Paste a generic clause. (defalias 'vhdl-port-paste-generic #[(&optional no-init) "\306 \307\211\211\211A@ \205\233�`\310\311!\210\204)�\312c\210\\j\210i \203\220� @\211@ \203J� @c\210 A\211\2035�\313c\210\2025�\314\nA@\261\210\204c�\315\n8\203c�\316\315\n8\261\210 A\204k�\317c\210\320c\210\203\200�\321\n8\203\200�\322\321\n8\323\"\210 A\211\203+�\312c\210 j\210\202+�\205\233�\324\f`\325\323$.\207" [vhdl-port-list generics-list generic names start list-margin current-indentation nil vhdl-insert-keyword "GENERIC (" "\n" ", " " : " 2 " := " ")" ";" 3 vhdl-comment-insert-inline t vhdl-align-noindent-region 1 margin vhdl-argument-list-indent vhdl-basic-offset no-init vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 252188)]) #@22 Paste a port clause. (defalias 'vhdl-port-paste-port #[nil "\306 \307\211\211\211\3108 \205\243�`\311\312!\210\204)�\313c\210\\j\210i \203\231� @\211A@\203?�\nA@\314\261\210\n@ \203W� @c\210 A\211\203B�\315c\210\202B�\316c\210\310\n8\203g�\310\n8\314\261\210\317\n8c\210 A\204t�\320c\210\321c\210\203\211�\322\n8\203\211�\323\322\n8\324\"\210 A\211\203+�\313c\210 j\210\202+�\205\243�\325\f`\326#.\207" [vhdl-port-list ports-list port names start list-margin current-indentation nil 2 vhdl-insert-keyword "PORT (" "\n" " " ", " " : " 3 ")" ";" 4 vhdl-comment-insert-inline t vhdl-align-noindent-region 1 margin vhdl-argument-list-indent vhdl-basic-offset vhdl-include-port-comments vhdl-auto-align] 8 (#$ . 252956)]) #@46 Paste as an entity or component declaration. (defalias 'vhdl-port-paste-declaration #[(kind) "\306 \210\307 @\310 \311=\203�\312\202�\313!\210 c\210 \311=\203$�\310\314!\210A@\203G�\315c\210\f\316>\203<� \311=\203<�\315c\210\n \\j\210\317 \320=!\210\3218\203d�\315c\210\f\322>\203_� \311=\203_�\315c\210\n \\j\210\323 \210\315c\210\f\324>\203y� \311=\203y�\315c\210\nj\210\310\325!\210 \311=\203\254�\326\326@=\206\234�\211A@)>)\204\244�\310\327!\210\330 \261\210\202\317�\310\331!\210\326\326@=\206\306�\211A@)>)\204\317�\330 \261\210\332c*\207" [vhdl-port-list name margin kind vhdl-insert-empty-lines vhdl-basic-offset vhdl-indent-line current-indentation vhdl-insert-keyword entity "ENTITY " "COMPONENT " " IS" "\n" (unit all) vhdl-port-paste-generic component 2 (unit all) vhdl-port-paste-port (unit all) "END" 87 " ENTITY" " " " COMPONENT" ";" standard vhdl-standard x] 3 (#$ . 253706)]) #@33 Paste as an entity declaration. (defalias 'vhdl-port-paste-entity #[nil "\204�\301\302!\207\303\304!\210\305\306!\210\303\307!\207" [vhdl-port-list error "No port read" message "Pasting port as entity..." vhdl-port-paste-declaration entity "Pasting port as entity...done"] 2 (#$ . 254635) nil]) #@35 Paste as a component declaration. (defalias 'vhdl-port-paste-component #[nil "\204�\301\302!\207\303\304!\210\305\306!\210\303\307!\207" [vhdl-port-list error "No port read" message "Pasting port as component..." vhdl-port-paste-declaration component "Pasting port as component...done"] 2 (#$ . 254938) nil]) #@25 Paste as a generic map. (defalias 'vhdl-port-paste-generic-map #[(&optional secondary no-constants) "\204�\306 \210\307 \310\211\211 A@\n\205\260�`\311\312!\210\204C�\n\205\260�\313\n@8\2060�\314c\210\nA\211\203=�\315\202>�\316c\210\202$�\204V�\317c\210\211\\\320\\\\j\210i\n\203\245�\n@\211@@\321\203n� @@\202u�\313 8\206u�\322\261\210\nA\211\203\203�\323\202\204�\316c\210\203\230�\324 8\203\230�\325\324 8\326\"\210\n\203X�\317c\210 j\210\202X�\205\260�\327\f`\330\326$-\207" [secondary vhdl-port-list generics-list generic start list-margin vhdl-indent-line current-indentation nil vhdl-insert-keyword "GENERIC MAP (" 2 " " ", " ")" "\n" 0 " => " "" "," 3 vhdl-comment-insert-inline t vhdl-align-noindent-region 1 margin vhdl-association-list-with-formals vhdl-argument-list-indent vhdl-basic-offset no-constants vhdl-include-port-comments vhdl-auto-align] 6 (#$ . 255255) nil]) #@22 Paste as a port map. (defalias 'vhdl-port-paste-port-map #[nil "\306 \307\211\211\3108 \205\301�`\311\312!\210\204;� \205\301�\313 @@@\"c\210 A\211\2035�\314\2026�\315c\210\202�\204M�\316c\210 \211\\\317\\\\j\210i \203\267� @\211@@\320\261\210\313\n@@\"c\210 A\211\203q�\321\202r�\315c\210\204\204� \203\252�\322\n8\203\252�\323\203\231�\324\325\310\n8\326P\206\225�\327\"\202\232�\327 \203\245�\322\n8\202\246�\327P\330\"\210 \203O�\316c\210\fj\210\202O�!\205\301�\331 `\332#-\207" [vhdl-port-list ports-list port start list-margin margin current-indentation nil 2 vhdl-insert-keyword "PORT MAP (" vhdl-replace-string ", " ");" "\n" 0 " => " "," 4 vhdl-comment-insert-inline format "%-4s" " " "" t vhdl-align-noindent-region 1 vhdl-association-list-with-formals vhdl-actual-port-name vhdl-argument-list-indent vhdl-basic-offset vhdl-include-direction-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 256172)]) #@28 Paste as an instantiation. (defalias 'vhdl-port-paste-instance #[(&optional name) "\204�\306\307!\207\310 \210\311 \210\312 \313\211\211\211A@\3148 \2034� \315\261\210\202N�!A\316\232\203D�\317\320\315\"\210\202N�\321!@\"\315\261\210\322\323!\210\324\"\324#@=\206h�\"#\211$A@)>)\203s�@c\210\202}�\325\326!\210\327@\261\210A@\203\222�\330c\210%\\j\210\331\332\211\"\210\3148\203\245�\330c\210%\\j\210\333 \210\322\334!\210. \211)\207" [vhdl-port-list orig-vhdl-port-list ports-list generics-list port generic error "No port read" vhdl-port-flatten vhdl-indent-line current-indentation nil 2 ": " "" vhdl-template-field "instance name" vhdl-replace-string message "Pasting port as instantiation..." 87 vhdl-insert-keyword "ENTITY " "work." "\n" vhdl-port-paste-generic-map t vhdl-port-paste-port-map "Pasting port as instantiation...done" start list-margin margin name vhdl-instance-name standard vhdl-standard x vhdl-basic-offset] 8 (#$ . 257131) nil]) #@34 Paste ports as internal signals. (defalias 'vhdl-port-paste-signals #[(&optional initialize) "\204�\306\307!\207\310\311!\210\312 \210\313 \314\211\211\3158 \203\257�` \203\244� @\211A@\2039� A@\316\261\210\202=�\317\320!\210 @\n\203Y�\321#\n@\"c\210\nA\211\203@�\322c\210\202@�\323\324 8\261\210$\203�\315 8\325\232\203�\326\327\330\324 8\"\203{�\331\202|�\332\261\210\333c\210%\203\224�\334 8\203\224�\335\334 8\336\"\210 A\211\203\"�\337c\210 j\210\202\"�&\203\257�\340\f`\341#\210-\310\342!\207" [vhdl-port-list ports-list names port start margin error "No port read" message "Pasting port as signals..." vhdl-indent-line current-indentation nil 2 " " vhdl-insert-keyword "SIGNAL " vhdl-replace-string ", " " : " 3 "in" " := " string-match "(.+)" "(others => '0')" "'0'" ";" 4 vhdl-comment-insert-inline t "\n" vhdl-align-noindent-region 1 "Pasting port as signals...done" vhdl-actual-port-name initialize vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 258130) nil]) #@30 Paste generics as constants. (defalias 'vhdl-port-paste-constants #[nil "\204�\306\307!\207\310\311!\210\312 \210\313 \210\314 \315\211\211A@\n\203\203�`\n\203x�\n@\316\317!\210\f@\211\203(� @c\210\320\fA@\261\210\321\f8\203R�\322\321\f8\261\210\323c\210\203g�\324\f8\203g�\325\324\f8\326\"\210\nA\211\203(�\327c\210j\210\202(�\203\203�\330 `\331#\210-\310\332!\210 \211)\207" [vhdl-port-list orig-vhdl-port-list generics-list name generic start error "No port read" message "Pasting port as constants..." vhdl-port-flatten vhdl-indent-line current-indentation nil vhdl-insert-keyword "CONSTANT " " : " 2 " := " ";" 3 vhdl-comment-insert-inline t "\n" vhdl-align-noindent-region 1 "Pasting port as constants...done" margin vhdl-include-port-comments vhdl-auto-align] 6 (#$ . 259134) nil]) #@35 Paste as a bare-bones test bench. (defalias 'vhdl-port-paste-testbench #[nil "\204�\306\307!\207\310\311!\210\312\313 @\"p\314\211\211\211\211;<=>?\315=\204\200�\316\317\320p!\"\210=\320p!\321\224\314OP\322 !\203t�\323\324 \325Q!\203d�\326 !\210\327 !\203t� q\210\330\314!\210\331 !\210\202t�?\332=\203p�\312\202t�\306\333!\210 \204\200�<q\210\334 !\210\321@?\332=\203\216� \204A\335\232\204\232�\336A!\210\337 \210\340c\210@j\210\341\342!\210\343c\210@j\210\341\344!\210\345c\210\341\346!\210\340c\210@j\210\337 \210\340c\210@j\210\341\347!\210=c\210\341\350!\210B\351>\203\341�\352c\210\352c\210@j\210\341\353!\210\354C\354D@=\206CD\211EA@)>)\204\n\341\347!\210=\355\261\210\340c\210@j\210\337 \210\352c\210FA\335\232\203.\356\357\314G#\2024\313F@\";?\332=\203\231\360 \210\316\317\320p!\"\210;\320p!\321\224\314OP\322\f!\203\323\324 \325Q!\203{\326\f!\210\327\f!\203\327\f!q\210\330\314!\210\331\f!\210\202\306\333!\210<q\210\334\f!\210H\335\232\204\223\336H!\210\337 \210\352c\210\352c\210@j\210\341\361!\210;c\210\341\362!\210=c\210\341\350!\210\340c\210@j\210\354C\354D@=\206\321CD\211EA@)>)\203\337\363 \210\340c\210@j\210A@\203\357\364 \210\340c\210@j\210\365I!\210J\335\232\204\340c\210\336J!\210\366 \210`\340c\210@j\210\337 \210\352c\210\nb\210\367\354C\354D@=\206/CD\211EA@)>)?\2055\370;@\312$\210\371\313K@\"!\210\352c\210L\335\232\204W\352c\210\336L!\210\352c\210@M\\j\210?\315=\204k\360 \210\310\372!. \207" [vhdl-port-list vhdl-testbench-entity-name position no-entity arch-file-name ent-file-name error "No port read" message "Pasting port as test bench..." t vhdl-replace-string nil none string-match "\\.[^.]*\\'" buffer-file-name 0 file-exists-p y-or-n-p "File `" "' exists; overwrite? " delete-file get-file-buffer set-buffer-modified-p kill-buffer separate "Pasting port as test bench...aborted" find-file "" vhdl-insert-string-or-file vhdl-comment-display-line "\n\n" vhdl-insert-keyword "LIBRARY " "ieee;\n" "USE " "ieee.std_logic_1164." "ALL;" "ENTITY " " IS" (unit all) "\n" "END " 87 ";" read-from-minibuffer "architecture name: " save-buffer "ARCHITECTURE " " OF " vhdl-port-paste-component vhdl-port-paste-constants vhdl-port-paste-signals delete-indentation vhdl-template-begin-end "ARCHITECTURE" vhdl-port-paste-instance "Pasting port as test bench...done" arch-name source-buffer ent-name case-fold-search vhdl-testbench-create-files margin vhdl-testbench-entity-header vhdl-insert-empty-lines standard vhdl-standard x vhdl-testbench-architecture-name vhdl-minibuffer-local-map vhdl-testbench-architecture-header vhdl-testbench-initialize-signals vhdl-testbench-declarations vhdl-testbench-dut-name vhdl-testbench-statements vhdl-basic-offset] 8 (#$ . 259953) nil]) (byte-code "\301B\302\301!\204\f�\303\303\207" [current-load-list vhdl-expand-upper-case boundp nil] 2) #@54 Try expanding abbreviations from `vhdl-abbrev-list'. (defalias 'vhdl-try-expand-abbrev #[(old) "\2042�\306\307 `\"\210 \310\211\203.� @;\203\"�\311\312\fP @\"\203'� @\nB A\211\204�\n\237* \203W� @;\203F�\313 @\314#\203W� @;\204P� @ A\211\2046� \204d�\203b�\315 \210\310\207\316\203p� @\226\202r� @\314\"\210 A\314\207" [old vhdl-abbrev-list sel-abbrev-list abbrev-list he-search-string he-expand-list he-init-string he-dabbrev-beg nil string-match "^" he-string-member t he-reset-string he-substitute-string he-tried-table vhdl-expand-upper-case] 5 (#$ . 262867)]) #@132 Also looks at the word before `(' in order to better match parenthesized expressions (e.g. for index ranges of types and signals). (defalias 'vhdl-he-list-beg #[nil "\212\300\301\302\217\210`)\207" [nil (byte-code "\300\301!\210\302\303!\207" [backward-up-list 1 skip-syntax-backward "w_"] 2) ((error))] 3 (#$ . 263455)]) (byte-code "\301\300!\203\n�\204�\302\303!\210\304\305\306\"\210\307\310M\210\311\312M\207" [viper-mode boundp require hippie-exp defalias he-list-beg vhdl-he-list-beg vhdl-expand-abbrev #[(arg) "\303\304\305\n!*\207" [hippie-expand-verbose hippie-expand-try-functions-list arg (try-expand-dabbrev try-expand-dabbrev-all-buffers vhdl-try-expand-abbrev) nil hippie-expand] 2 "Try to expand text before point, using the following functions: \ntry-expand-dabbrev, try-expand-dabbrev-all-buffers, vhdl-try-expand-abbrev" "P"] vhdl-expand-paren #[(arg) "\303\304\305\n!*\207" [hippie-expand-verbose hippie-expand-try-functions-list arg (try-expand-list try-expand-list-all-buffers) nil hippie-expand] 2 "Try to expand text before point, using the following functions: \ntry-expand-list, try-expand-list-all-buffers" "P"]] 3) #@109 Convert all words matching word-regexp in region to lower or upper case, depending on parameter upper-case. (defalias 'vhdl-fix-case-region-1 #[(beg end upper-case word-regexp &optional count) "\306\307\310\307\311\312\313\f#\210\212 b\210\314 b\210\315 \306#\203\212�`\212\316 \210\315\317\306#*\204W�`\212\316 \210\315\320\306#*=\204W�\203S�\321\322!\210\202W�\323\322!\210\203� \203� \324 A@ZW\203�\325\326\327_`Z\327_ Z\245\\\330#\210\324 A@\202� b)!\204\231�\311\312\331\f#\210 \210)\205\251� \205\251�\325\332!+\207" [last-update case-replace case-fold-search result vhdl-mode-syntax-table end t nil 0 modify-syntax-entry 95 "w" point-marker re-search-forward beginning-of-line "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*--" "^\\([^\"]*\"[^\"]*\"\\)*[^\"]*\"[^\"]*" upcase-word -1 downcase-word current-time message "Fixing case... (%2d%s)" 25 "%" "_" "Fixing case...done" beg word-regexp position upper-case count vhdl-progress-interval vhdl-underscore-is-part-of-word] 6 (#$ . 264610)]) #@138 Convert all VHDL words in region to lower or upper case, depending on variables vhdl-upper-case-{keywords,types,attributes,enum-values}. (defalias 'vhdl-fix-case-region #[(beg end &optional arg) "\306 \n \307%\210\306 \f \310%\210\306 \f\311 P\312%\210\306 \313%\207" [beg end vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-fix-case-region-1 0 1 "'" 2 3 vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp] 6 (#$ . 265642) "r\nP"]) #@138 Convert all VHDL words in buffer to lower or upper case, depending on variables vhdl-upper-case-{keywords,types,attributes,enum-values}. (defalias 'vhdl-fix-case-buffer #[nil "\300ed\"\207" [vhdl-fix-case-region] 3 (#$ . 266185) nil]) #@54 Return the line number of the line containing point. (defalias 'vhdl-current-line #[nil "\214~\210\212\300 \210\301\302`\"T*\207" [beginning-of-line count-lines 1] 3 (#$ . 266426)]) #@21 Delete entire line. (defalias 'vhdl-line-kill-entire #[(&optional arg) "\301 \210\302\206 �\303!\207" [arg beginning-of-line kill-line 1] 2 (#$ . 266614) "p"]) #@20 Kill current line. (defalias 'vhdl-line-kill #[(&optional arg) "\301!\207" [arg vhdl-line-kill-entire] 2 (#$ . 266781) "p"]) #@20 Copy current line. (defalias 'vhdl-line-copy #[(&optional arg) "\212\302 \210` \206 �\303y\210\304`\"*\207" [position arg beginning-of-line 1 copy-region-as-kill] 3 (#$ . 266913) "p"]) #@19 Yank entire line. (defalias 'vhdl-line-yank #[nil "\300 \210\301 \207" [beginning-of-line yank] 1 (#$ . 267106) nil]) #@29 Hippie-expand current line. (defalias 'vhdl-line-expand #[(&optional prefix-arg) "\304\305\306\307 !+\207" [hippie-expand-try-functions-list case-replace case-fold-search prefix-arg t nil (try-expand-line try-expand-line-all-buffers) hippie-expand] 3 (#$ . 267230) "P"]) #@39 Interchange this line with next line. (defalias 'vhdl-line-transpose-next #[(&optional arg) "\301y\210\302\206 �\301!\210\303y\207" [arg 1 transpose-lines -1] 2 (#$ . 267510) "p"]) #@43 Interchange this line with previous line. (defalias 'vhdl-line-transpose-previous #[(&optional arg) "\301y\210\302\206 �\303[!\210\304y\207" [arg 1 transpose-lines 0 -1] 2 (#$ . 267698) "p"]) #@29 Open a new line and indent. (defalias 'vhdl-line-open #[nil "\300\210\301 \207" [0 newline-and-indent] 1 (#$ . 267897) nil]) #@25 Switch to project NAME. (defalias 'vhdl-project-switch #[(name) "\303\302!\205�\304\n!\205�\305 \207" [name vhdl-project speedbar-frame boundp frame-live-p speedbar-refresh] 2 (#$ . 268029)]) #@29 Initialize for compilation. (defalias 'vhdl-compile-init #[nil "\204C� \306\211\211\203@�\307\f@8\211@\310\232\2049�\n@\nA@\311U\203/�\312\313 \"\2052�\314\2022�\nA@\315\n8E B\fA\211\204� +?\205p� \306\211\203k�\316\f@8@\310\232\204d�\317 \316\f@8C\"\fA\211\204Q� *\211\207" [compilation-error-regexp-alist vhdl-compiler-alist sublist regexp-alist commands-alist emacs-version nil 5 "" 0 string-match "XEmacs" 9 2 6 append compilation-file-regexp-alist] 5 (#$ . 268231)]) #@78 Compile current buffer using the VHDL compiler specified in `vhdl-compiler'. (defalias 'vhdl-compile #[nil "\306 \210\307 \"\211A@\310\311\n8! \205'�\312 \313 \211\314\230?\205\"�\313\315 \260!+\207" [vhdl-compiler vhdl-compiler-alist command-elem command default-directory vhdl-compiler-options vhdl-compile-init assoc expand-file-name 4 compile " " "" buffer-file-name] 7 (#$ . 268726) nil]) #@86 Call make command for compilation of all updated source files (requires `Makefile'). (defalias 'vhdl-make #[nil "\305 \210\306 \"\307\n8\310\311\n8! \312\232\203�\313\314!\202!�\313 !+\207" [vhdl-compiler vhdl-compiler-alist command-elem command default-directory vhdl-compile-init assoc 2 expand-file-name 4 "" compile "make"] 3 (#$ . 269131) nil]) #@26 Generate new `Makefile'. (defalias 'vhdl-generate-makefile #[nil "\305 \210\306 \"\307\n8\310\311\n8! \312\232\204�\313 !\202\"�\314\315\"+\207" [vhdl-compiler vhdl-compiler-alist command-elem command default-directory vhdl-compile-init assoc 3 expand-file-name 4 "" compile error "No such command specified for `%s'"] 3 (#$ . 269492) nil]) #@57 Find begin and end of VHDL design units (for hideshow). (defalias 'vhdl-forward-unit #[(&optional count) "\302 \303W\203�\304\305\306\302#\202�\307\310\306\302#)\207" [case-fold-search count t 0 re-search-backward "^\\(architecture\\|configuration\\|entity\\|package\\)\\>" nil re-search-forward "^end\\>"] 4 (#$ . 269845) "p"]) (byte-code "\302\303\"\203 �\304\305!\210\306 \236\204�\307 B\302\207" [emacs-version hs-special-modes-alist string-match "XEmacs" require hideshow vhdl-mode (vhdl-mode "\\(^\\)\\(architecture\\|ARCHITECTURE\\|configuration\\|CONFIGURATION\\|entity\\|ENTITY\\|package\\|PACKAGE\\)\\>" "\\(^\\)\\(end\\|END\\)\\>" "--\\( \\|$\\)" vhdl-forward-unit)] 3) #@24 Initialize `hideshow'. (defalias 'vhdl-hideshow-init #[nil "\203\f�\302\303\304\"\210\202�\305\303\304\"\210 \203�\306\307!\207\310\306!\205\"�\306\311!\207" [vhdl-hide-all-init vhdl-hideshow-menu add-hook hs-minor-mode-hook hs-hide-all remove-hook hs-minor-mode 1 boundp 0] 3 (#$ . 270538)]) #@56 Return point if within translate-off region, else nil. (defalias 'vhdl-within-translate-off #[nil "\212\300\301\302\303#)\205�\304\305!\306\232\205�`\207" [re-search-backward "^\\s-*--\\s-*pragma\\s-*translate_\\(on\\|off\\)\\s-*\n" nil t match-string 1 "off"] 4 (#$ . 270840)]) #@69 Return point before translate-off pragma if before LIMIT, else nil. (defalias 'vhdl-start-translate-off #[(limit) "\301\302\303#\205\n�\304\224\207" [limit re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_off\\s-*\n" t 0] 4 (#$ . 271127)]) #@67 Return point after translate-on pragma if before LIMIT, else nil. (defalias 'vhdl-end-translate-off #[(limit) "\301\302\303#\207" [limit re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_on\\s-*\n" t] 4 (#$ . 271378)]) #@76 Match a translate-off block, setting match-data and returning t, else nil. (defalias 'vhdl-match-translate-off #[(limit) "`W\205'�\304 \206�\305!\306\211\205&�\307!\206�\310\n D!\210 b)*\207" [limit case-fold-search start end vhdl-within-translate-off vhdl-start-translate-off t vhdl-end-translate-off set-match-data] 4 (#$ . 271607)]) #@131 Match, and move over, any declaration item after point. Adapted from `font-lock-match-c-style-declaration-item-and-skip-to-next'. (defalias 'vhdl-font-lock-match-item #[(limit) "\300\301\302\217\207" [nil (byte-code "\214e}\210\302\303!\205%�\304 \305\216\306\225b\210\302\307!\203 �\306\225b\202$�\310\210\311*)\207" [limit save-match-data-internal looking-at "\\s-*\\(\\w+\\)" match-data ((set-match-data save-match-data-internal)) 1 "\\(\\s-*,\\)" nil t] 2) ((error t))] 3 (#$ . 271959)]) #@68 Mark single quotes as having string quote syntax in 'c' instances. (defconst vhdl-font-lock-syntactic-keywords '(("\\('\\).\\('\\)" (1 (7 . 39)) (2 (7 . 39)))) (#$ . 272460)) #@48 Regular expressions to highlight in VHDL Mode. (defvar vhdl-font-lock-keywords nil (#$ . 272641)) #@129 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of template prompts and directives (pragmas). (defconst vhdl-font-lock-keywords-0 (byte-code "\301\302Q\303\304\305F\306D\207" [vhdl-template-prompt-syntax "\\(<" ">\\)" 1 vhdl-font-lock-prompt-face t ("--\\s-*pragma\\s-+\\(.*\\)$" 1 vhdl-font-lock-directive-face t)] 4) (#$ . 272746)) #@121 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of keywords and standard identifiers. (defvar vhdl-font-lock-keywords-1 nil (#$ . 273122)) #@122 For consideration as a value of `vhdl-font-lock-keywords'. This does context sensitive highlighting of names and labels. (defconst vhdl-font-lock-keywords-2 (byte-code "\303\304\305E\306\307\305E\310\311\312\313\313 @=\206� \211A@)>)\205!�\314\315\316\260\317\305E\320\321\322E\323\324\325\326\313\313 @=\206A� \211A@)>)\205F�\314\327\330\260\304\305E\331\332\305E\333\317\305E\334\335\336E\337\317\340E\341\332\342E\343\344D\345\346D\257\f\207" [standard vhdl-standard x "^\\s-*\\(architecture\\|configuration\\|entity\\|package\\(\\s-+body\\|\\)\\|\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\|component\\)\\s-+\\(\\w+\\)" 5 font-lock-function-name-face "^\\s-*\\(architecture\\|configuration\\)\\s-+\\w+\\s-+of\\s-+\\(\\w+\\)" 2 "^\\s-*\\(\\w+\\)\\s-*:\\(\\s-\\|\n\\)*\\(\\(" "assert\\|block\\|case\\|component\\|configuration\\|entity\\|exit\\|" "for\\|if\\|loop\\|next\\|null\\|postponed\\|process\\|" ams "procedural\\|" "with\\|while" "\\)\\>\\|[^\n]*<=\\)" 1 "^\\s-*\\(\\w+\\)\\s-*:[ \n]*\\(component\\s-+\\|\\)\\(\\w+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>" (1 font-lock-function-name-face) (3 font-lock-function-name-face) "^\\s-*end\\s-+\\(\\(" "architecture\\|block\\|case\\|component\\|configuration\\|entity\\|" "for\\|function\\|generate\\|if\\|loop\\|package\\(\\s-+body\\|\\)\\|" "procedure\\|\\(postponed\\s-+\\|\\)process\\|" "units" "\\)\\>\\|\\)\\s-*\\(\\w*\\)" "^\\s-*\\(\\w+\\s-*:\\s-*\\)?\\(exit\\|next\\)\\s-+\\(\\w*\\)" 3 "^\\s-*attribute\\s-+\\w+\\s-+of\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\s-*:" "^\\s-*for\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\s-*:\\(\\s-\\|\n\\)*\\(\\w+\\)" (1 font-lock-function-name-face) (4 font-lock-function-name-face) "^\\s-*attribute\\s-+\\(\\w+\\)" vhdl-font-lock-attribute-face "^\\s-*\\(sub\\|\\)\\(nature\\|type\\)\\s-+\\(\\w+\\)" font-lock-type-face "\\(:[^=]\\)" (vhdl-font-lock-match-item (progn (goto-char (match-beginning 1)) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " ") (while (= (preceding-char) 44) (backward-char 1) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " "))) (goto-char (match-end 1)) (1 font-lock-variable-name-face)) "\\<\\(alias\\|for\\|group\\)\\s-+\\w+\\s-+\\(in\\|is\\)\\>" (vhdl-font-lock-match-item (progn (goto-char (match-end 1)) (match-beginning 2)) nil (1 font-lock-variable-name-face))] 13) (#$ . 273302)) #@113 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of words with special syntax. (defvar vhdl-font-lock-keywords-3 nil (#$ . 275695)) #@113 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of additional reserved words. (defvar vhdl-font-lock-keywords-4 nil (#$ . 275867)) #@120 For consideration as a value of `vhdl-font-lock-keywords'. This does background highlighting of translate-off regions. (defconst vhdl-font-lock-keywords-5 '((vhdl-match-translate-off (0 vhdl-font-lock-translate-off-face append))) (#$ . 276039)) #@31 Face name to use for prompts. (defvar vhdl-font-lock-prompt-face 'vhdl-font-lock-prompt-face (#$ . 276290)) #@47 Face name to use for standardized attributes. (defvar vhdl-font-lock-attribute-face 'vhdl-font-lock-attribute-face (#$ . 276404)) #@55 Face name to use for standardized enumeration values. (defvar vhdl-font-lock-enumvalue-face 'vhdl-font-lock-enumvalue-face (#$ . 276540)) #@59 Face name to use for standardized functions and packages. (defvar vhdl-font-lock-function-face 'vhdl-font-lock-function-face (#$ . 276684)) #@34 Face name to use for directives. (defvar vhdl-font-lock-directive-face 'vhdl-font-lock-directive-face (#$ . 276830)) #@49 Face name to use for additional reserved words. (defvar vhdl-font-lock-reserved-words-face 'vhdl-font-lock-reserved-words-face (#$ . 276953)) #@45 Face name to use for translate-off regions. (defvar vhdl-font-lock-translate-off-face 'vhdl-font-lock-translate-off-face (#$ . 277101)) (byte-code "\303\211\203&�\304\305\n@@\306#\307\310 \311 D\312\n@@\313QF!\210\nA\211\204�*\314\315\303\316\317\320%\210\321\315\322\323#\210\321\315\324\323#\210\321\315\325\323#\210\321\315\326\323#\210\321\315\327\323#\210\321\315\330\323#\210\331\332\333\334\317\315\317\335&\210\331\336\337\340\317\315\317\335&\210\331\341\342\343\317\315\317\335&\210\331\344\345\346\317\315\317\335&\210\331\347\350\351\317\315\317\335&\210\331\352\353\354\317\315\317\335&\210\331\355\356\357\317\315\317\335&\210\211\203\330�\307\360\304\305\n@@\306#\311\361\362\363\n@8DD\364\362\365\n@8DD\366BBD\367\n@@\313Q\370BBBB!\210\nA\211\204\246�)\303\207" [vhdl-special-syntax-alist name syntax-alist nil vhdl-function-name "vhdl-font-lock" "face" eval defvar quote "Face name to use for " "." custom-declare-group vhdl-highlight-faces "Faces for highlighting." :group vhdl-highlight custom-add-to-group font-lock-comment-face custom-face font-lock-string-face font-lock-keyword-face font-lock-type-face font-lock-function-name-face font-lock-variable-name-face custom-declare-face vhdl-font-lock-prompt-face ((((class color) (background light)) (:foreground "Red" :bold t)) (((class color) (background dark)) (:foreground "Pink" :bold t)) (t (:inverse-video t))) "Font lock mode face used to highlight prompts." font-lock-highlighting-faces vhdl-font-lock-attribute-face ((((class color) (background light)) (:foreground "Orchid")) (((class color) (background dark)) (:foreground "LightSteelBlue")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized attributes." vhdl-font-lock-enumvalue-face ((((class color) (background light)) (:foreground "Gold4")) (((class color) (background dark)) (:foreground "BurlyWood")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized enumeration values." vhdl-font-lock-function-face ((((class color) (background light)) (:foreground "Orchid4")) (((class color) (background dark)) (:foreground "Orchid1")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized functions and packages." vhdl-font-lock-directive-face ((((class color) (background light)) (:foreground "CadetBlue")) (((class color) (background dark)) (:foreground "Aquamarine")) (t (:italic t :bold t))) "Font lock mode face used to highlight directives." vhdl-font-lock-reserved-words-face ((((class color) (background light)) (:foreground "Orange" :bold t)) (((class color) (background dark)) (:foreground "Yellow" :bold t)) (t nil)) "Font lock mode face used to highlight additional reserved words." vhdl-font-lock-translate-off-face ((((class color) (background light)) (:background "LightGray")) (((class color) (background dark)) (:background "DimGray")) (t nil)) "Font lock mode face used to background highlight translate-off regions." defface ((class color) (background light)) :foreground 2 ((class color) (background dark)) 3 ((t nil)) "Font lock mode face used to highlight " (:group 'vhdl-highlight-faces :group 'font-lock-highlighting-faces)] 10) #@27 Initialize fontification. (defalias 'vhdl-font-lock-init #[nil "\306P\307\310E \307\311E\n\307\312E \307\312E\f\307\313E \307\314E\257\315\211\203H�\316@A@\317Q\320\321@@\322#BBA\211\204)�*\307\323EC\324\205_�\204i�\205k� \205r�!\205y�\"#\205\200�$&\211%\207" [vhdl-attributes-regexp vhdl-types-regexp vhdl-functions-regexp vhdl-packages-regexp vhdl-enum-values-regexp vhdl-keywords-regexp "'" 1 vhdl-font-lock-attribute-face font-lock-type-face vhdl-font-lock-function-face vhdl-font-lock-enumvalue-face font-lock-keyword-face nil "\\<\\(" "\\)\\>" vhdl-function-name "vhdl-font-lock" "face" vhdl-font-lock-reserved-words-face append vhdl-font-lock-keywords-1 vhdl-special-syntax-alist keywords syntax-alist vhdl-font-lock-keywords-3 vhdl-reserved-words-regexp vhdl-font-lock-keywords-4 vhdl-font-lock-keywords-0 vhdl-highlight-keywords vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-special-words vhdl-highlight-names vhdl-font-lock-keywords-2 vhdl-highlight-translate-off vhdl-font-lock-keywords-5 vhdl-font-lock-keywords] 9 (#$ . 280277)]) (vhdl-font-lock-init) #@49 Re-initialize fontification and fontify buffer. (defalias 'vhdl-fontify-buffer #[nil "\302\303?\304\305\306\257\307\310!\203�\310 \210\311 \210\312 \207" [vhdl-highlight-case-sensitive font-lock-defaults vhdl-font-lock-keywords nil ((95 . "w")) beginning-of-line (font-lock-syntactic-keywords . vhdl-font-lock-syntactic-keywords) fboundp font-lock-unset-defaults font-lock-set-defaults font-lock-fontify-buffer] 6 (#$ . 281431) nil]) #@67 Initialize custom face and page settings for postscript printing. (defalias 'vhdl-ps-print-settings #[nil "\203� \204�\305\306!\307L\210\305\310!\311L\210\305\312!\313L\210\314 \205[�\305\315!\314L\210\305\316!\317L\210\305\320!\321L\210\305\322!\323L\210\305\324!\325L\210\305\326!\327L\210\f\330=\205[�\305\331!\332L\210\305\333!\334L\210\305\335!\336L\207" [vhdl-print-customize-faces ps-print-color-p ps-always-build-face-reference vhdl-print-two-column ps-paper-type make-local-variable ps-bold-faces (font-lock-keyword-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) ps-italic-faces (font-lock-comment-face font-lock-function-name-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) ps-underlined-faces (font-lock-string-face) t ps-landscape-mode ps-number-of-columns 2 ps-font-size 7.0 ps-header-title-font-size 10.0 ps-header-font-size 9.0 ps-header-offset 12.0 letter ps-inter-column 40.0 ps-left-margin 40.0 ps-right-margin 40.0] 2 (#$ . 281875)]) #@33 Initialize postscript printing. (defalias 'vhdl-ps-print-init #[nil "\301\302\"\203\n�\303 \207\304\305!\210\306\305\303\"\207" [emacs-version string-match "XEmacs" vhdl-ps-print-settings make-local-variable ps-print-hook add-hook] 3 (#$ . 282975)]) #@100 Cache with entities and corresponding architectures and configurations for each visited directory. (defvar vhdl-entity-alist nil (#$ . 283233)) #@49 Cache with packages for each visited directory. (defvar vhdl-package-alist nil (#$ . 283383)) #@62 Cache with instantiated entities for each visited directory. (defvar vhdl-ent-inst-alist nil (#$ . 283483)) #@98 Cache with entities and corresponding architectures and configurations for each visited project. (defvar vhdl-project-entity-alist nil (#$ . 283597)) #@49 Cache with packages for each visited directory. (defvar vhdl-project-package-alist nil (#$ . 283753)) #@62 Cache with instantiated entities for each visited directory. (defvar vhdl-project-ent-inst-list nil (#$ . 283861)) #@99 Alist of design units simultaneously open in the current speedbar for each directory and project. (defvar vhdl-speedbar-shown-units-alist nil (#$ . 283982)) #@52 Last file for which design units were highlighted. (defvar vhdl-speedbar-last-file-name nil (#$ . 284145)) #@39 Cache with design units in each file. (defvar vhdl-file-alist nil (#$ . 284258)) #@84 Return non-nil if a project is displayed, i.e. directories or files are specified. (defalias 'vhdl-speedbar-project-p #[nil "\302 \"A@\207" [vhdl-project-alist vhdl-project aget] 3 (#$ . 284345)]) (put 'vhdl-speedbar-project-p 'byte-optimizer 'byte-compile-inline-expand) #@43 Scan contents of VHDL files in FILE-LIST. (defalias 'vhdl-scan-file-contents #[(name &optional num-string) "\306\307\"\210\310\224\310\225U\211\203�\311\312\"\237\202$�\313\314\315\"\312\316\314\310\"!#\312p\317\3171\317<\317= \204A�\n\204A�\320\321\"\210\212\n\205\347\nG=\n\203\243\320\322 \203X�\323\202Y�\324>\206_�\325=\nGZ\326_=\245\327&\210\330\n@!\317\211\211\211\211\211\211\211?@ABCDEFG\331G!\203\234�\331G!q\210\202\247�\332G\317\312#q\210\312F\333\334\335\336 #\210eb\210\337\340\317\312#\203\353�\341 \314\315!\"H\310H8'\342H8/\314\315!CBC\343\305\314\315!G\344 '/\317\257#\210+\202\261�eb\210\337\345\317\312#\203\325\314\310!\203I\341 \314\342!\"H\310H8'\342H8/\314\310!E\314\342!DEBBB\346\347EG\344 \317E#\210H@HA@'/\317\257H\343\305DH#\210+\202\356�\341 D\"H\310H8'\341'E\"I\310I8-\314\350!J\314\351!K\314\352!L\342H8/\353\354\317\312#\210J?B?\346\355JG\344 KLF#\210I@IA@-EI\346\347EI#\210H@HA@'/\317\257H\343\305DH#\210K<\235\204\320K<B<.\202\356�eb\210\337\356\317\312#\203%\341 \314\310!\"H\310H8'\342H8/\314\315!ABA\346\357\314\315!G\344 D#\210H@HA@'/\317\257H\343\305\314\310!H#\210+\202\330eb\210\337\360\317\312#\203n\3411\314\310!\"M\314\310!@B@\343\361\314\310!\314\315!\204\\G\344 \310M8\342M8F\202hM@MA@G\344 F#\210)\202(\nA\343\362GCBA@?\257#\210F\203\217\363p!\210\202\233N\204\233\333\334\364O#\210\fq\210. \202J�\365 \366\"\3651\367\"1 \203\271\343\370 #\2101\203\305\343\3711#\210<\203\322\343\372<C#\210\320\373 \203\334\323\202\335\324>\206\343\325$\210\312. \207" [name is-directory file-list case-fold-search source-buffer ent-alist string-match "\\(.*/\\)\\(.*\\)" 2 vhdl-get-source-files t vhdl-directory-files match-string 1 wildcard-to-regexp nil message "No such file: \"%s\"" "Scanning %s %s\"%s\"... (%2d%s)" "directory" "files" "" 100 "%" abbreviate-file-name find-buffer-visiting find-file-noselect modify-syntax-entry 95 "w" syntax-table re-search-forward "^\\s-*entity\\s-+\\(\\w+\\)" aget 3 aput vhdl-current-line "^\\s-*\\(architecture\\s-+\\(\\w+\\)\\s-+of\\s-+\\(\\w+\\)\\|\\(\\w+\\)\\s-*:\\(\\s-\\|\n\\)*\\(entity\\s-+\\w+\\.\\)?\\(\\w+\\)\\(\\s-*(\\(\\w+\\))\\)?\\(\\s-\\|\n\\|--.*\n\\)*\\(generic\\|port\\)\\s-+map\\>\\)" vhdl-aappend arch-alist 4 7 9 re-search-backward ":" inst-alist "^\\s-*configuration\\s-+\\(\\w+\\)\\s-+of\\s-+\\(\\w+\\)" conf-alist "^\\s-*package\\s-+\\(body\\s-+\\)?\\(\\w+\\)" pack-alist vhdl-file-alist kill-buffer "_" sort #[(a b) "@ @\231\207" [a b] 2] #[(a b) "@ @\231\207" [a b] 2] vhdl-entity-alist vhdl-package-alist vhdl-ent-inst-alist "Scanning %s %s\"%s\"...done" ent-inst-list no-files num-string inst-list pack-list conf-list arch-list ent-list ent-name arch-name opened file-name ent-entry arch-entry inst-name inst-ent-name inst-arch-name pack-entry vhdl-underscore-is-part-of-word vhdl-mode-syntax-table] 10 (#$ . 284624)]) #@84 Scan the contents of all VHDL files found in the directories and files of PROJECT. (defalias 'vhdl-scan-project-contents #[(project &optional rescan) "\306 \"A@\307\211\211\211\211\211\211\211 !\"\310\"!\211\"\203Q�\"@\311\312 \"\203@�\313!\314\315\316 \"!\"!\202H�\313! C\"!\"A\211\"\204&�!G\316!\203M\317!@!#\204w�\320\f$\"\204\200�\320\f%\"\204\200�\321\f\322\323\n #\"\210\306$\f\"\211&\203\330�&@@'&@A(\306'\")\324\325')@\206\254�(@)A@\206\267�(A@\313\326)8\326(8\"\313\327)8\327(8\"F#\210+&A\211&\204\213�)\306%\f\"\211*\2033*@@+*@A,\306+\"-\324\330+-@\206,@-A@\206,A@\326-8\206\326,8\327-8\206&\327,8F#\210+*A\211*\204\344�)\313 \331\306.\f\"@!\" !A!\nT\202W�\203\\\324\332 \333\334\"#\210\203k\324\335 \333\336\"#\210 \205v\324\337  #. \207" [vhdl-project-alist project act-dir num-dir name dir aget nil vhdl-resolve-paths string-match "-r \\(.*/\\)" append vhdl-get-subdirs match-string 1 abbreviate-file-name assoc vhdl-scan-file-contents format "(%s/%s) " aput pro-ent-alist 2 3 pro-pack-alist copy-alist vhdl-project-entity-alist sort #[(a b) "@ @\231\207" [a b] 2] vhdl-project-package-alist #[(a b) "@ @\231\207" [a b] 2] vhdl-project-ent-inst-list pro-ent-inst-list dir-list dir-list-tmp rescan vhdl-entity-alist vhdl-package-alist ent-alist ent-name ent-entry pro-ent-entry pack-alist pack-name pack-entry pro-pack-entry vhdl-ent-inst-alist] 11 (#$ . 287625)]) #@85 Get instantiation hierarchy beginning in architecture ARCH-NAME of entity ENT-NAME. (defalias 'vhdl-get-hierarchy #[(ent-name arch-name level indent &optional ent-hier) "\306 \"A@\203�\306\n \"\202�\306 \307\310\311\fS!!!\"\306 \"\2033�\306\3128\"\202;�\313\3128!@A\3128\314\314\314\314 !\315U\203Z�\316\317!\210\"\235\203j�\320\321\322\"!\210\203\352�@\306 \3238\"\3248\203\226�\3248\306\3128\3248\"B\202\235�\313\3128!@\325 @A@\3128B\3238@A@B@A@\3128B!\257\326\3238\3248!T\f\"B%B\" A\211\204o�!\315U\203\365�\316\327!\210 .\207" [vhdl-project-alist vhdl-project vhdl-project-entity-alist vhdl-entity-alist indent ent-alist aget abbreviate-file-name file-name-as-directory speedbar-line-path 2 last nil 0 message "Extract design hierarchy..." error format "Instantiation loop detected; component \"%s\" instantiates itself" 3 4 append vhdl-get-hierarchy "Extract design hierarchy...done" ent-name ent-entry arch-name arch-entry inst-list inst-entry inst-ent-entry inst-arch-entry hier-list level ent-hier] 11 (#$ . 289111)]) #@44 Get all instantiations of entity ENT-NAME. (defalias 'vhdl-get-instantiations #[(ent-name indent) "\306 \"A@\203�\306\n \"\202�\306 \307\310\311\f!!!\"\312\211\211\211\211\211 \211\203\237�@\3138\211\203\226�@ \313 8\211\203\215�@\313 8\232\203\204� @ A@\314 8B@A@\3148B @ A@\314 8B\257BA\211\204O�A\211\204@�A\211\2041�\237.\207" [vhdl-project-alist vhdl-project vhdl-project-entity-alist vhdl-entity-alist indent inst-entry aget abbreviate-file-name file-name-as-directory speedbar-line-path nil 3 2 arch-entry ent-entry ent-inst-list inst-alist arch-alist ent-alist ent-name] 9 (#$ . 290237)]) #@54 Keymap used when in the VHDL hierarchy browser mode. (defvar vhdl-speedbar-key-map nil (#$ . 290903)) #@49 Additional menu-items to add to speedbar frame. (defvar vhdl-speedbar-menu-items '(["Edit Design Unit" speedbar-edit-line t] ["Expand Hierarchy" speedbar-expand-line (save-excursion (beginning-of-line) (looking-at "[0-9]+: *.\\+. "))] ["Contract Hierarchy" speedbar-contract-line (save-excursion (beginning-of-line) (looking-at "[0-9]+: *.-. "))] ["Rescan Hierarchy" vhdl-speedbar-rescan-hierarchy t] "--" ["Copy Port" vhdl-speedbar-port-copy (save-excursion (beginning-of-line) (looking-at "[0-9]+: *\\[[-+?]\\] "))]) (#$ . 291011)) #@22 Initialize speedbar. (defalias 'vhdl-speedbar-initialize #[nil "\211\203� @A\306=\203�\307 @@!\210 A\211\204�)\310\311!\205g�\312\313!\210\n\204Q�\314 \315\n\316\317#\210\315\n\320\317#\210\315\n\321\322#\210\315\n\323\324#\210\315\n\325\326#\210\315\n\327\330#\210\315 \331\332#\210\333\334!\210\335\fB \205g�\336\211\207" [auto-mode-alist mode-alist vhdl-speedbar-key-map speedbar-key-map speedbar-stealthy-function-list vhdl-speedbar-show-hierarchy vhdl-mode speedbar-add-supported-extension boundp speedbar-mode-functions-list speedbar-add-mode-functions-list ("vhdl hierarchy" (speedbar-item-info . vhdl-speedbar-item-info) (speedbar-line-path . speedbar-files-line-path)) speedbar-make-specialized-keymap define-key "e" speedbar-edit-line " " "+" speedbar-expand-line "-" speedbar-contract-line "s" vhdl-speedbar-rescan-hierarchy "c" vhdl-speedbar-port-copy "h" #[nil "\300\301!\207" [speedbar-change-initial-expansion-list "vhdl hierarchy"] 2 nil nil] speedbar-add-expansion-list ("vhdl hierarchy" vhdl-speedbar-menu-items vhdl-speedbar-key-map vhdl-speedbar-display-hierarchy) ("vhdl hierarchy" vhdl-speedbar-update-current-unit) "vhdl hierarchy" speedbar-initial-expansion-list-name] 5 (#$ . 291551)]) #@22 Open/close speedbar. (defalias 'vhdl-speedbar #[(&optional arg) "\300\301!\204\n�\302\303!\207\304\305\306\217\207" [fboundp speedbar error "WARNING: Speedbar is only available in newer Emacs versions" nil (speedbar-frame-mode arg) ((error (error "WARNING: Install included `speedbar.el' patch first")))] 3 (#$ . 292778) nil]) (byte-code "\301\300!\204�\302\303\304\"\210\202�\304 \210\203�\305 \210\301\207" [speedbar-frame boundp add-hook speedbar-load-hook vhdl-speedbar-initialize speedbar-refresh] 3) #@53 Allow the buffer to be writable and evaluate FORMS. (defalias 'speedbar-with-writable '(macro . #[(&rest forms) "\301\302\303BE\207" [forms let ((inhibit-read-only t)) progn] 4 (#$ . 293296)])) (put 'speedbar-with-writable 'lisp-indent-function 0) #@58 Display directory and hierarchy information in speedbar. (defalias 'vhdl-speedbar-display-hierarchy #[(directory depth &optional rescan) "\306\307!!\310\311\212\312 \f\"A@\203?�\313\314\315\"\210`\316c\210\317 `\320\311$\210`\fc\210\317 `\321\322$\210)\323\324\325\"\210\326\f\"\202_�\327\"\210\330\331!\"\210\332#\210\315U\205_�\333!*\207" [directory speedbar-last-selected-file inhibit-read-only vhdl-project-alist vhdl-project start abbreviate-file-name file-name-as-directory nil t aget vhdl-speedbar-make-title-line "Project:" 0 "p:" put-text-property invisible face speedbar-directory-face insert-char 10 1 vhdl-speedbar-insert-project-hierarchy speedbar-directory-buttons vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy vhdl-speedbar-expand-dirs speedbar-power-click depth] 5 (#$ . 293551)]) #@47 Insert hierarchy of ENT-ALIST and PACK-ALIST. (defalias 'vhdl-speedbar-insert-hierarchy #[(ent-alist pack-alist ent-inst-list depth) "\204 � \204 �\306\307\n\"\207\310\211\203�\306\311\n\"\210\203M�@\312\313\314\315\f@\f@\316\fA@\317\f8B\320\n& \210\f@ \235\204F�\321\210\322c\210\323u\210A\211\204� \203V�\306\324\n\"\210 \205y� @\325 @ A@\317 8B\326 8\327 8B\n$\210 A\211\204Z�\310*\207" [ent-alist pack-alist depth pack-entry ent-entry ent-inst-list vhdl-speedbar-make-title-line "No design units!" nil "Entities:" speedbar-make-tag-line bracket 43 vhdl-speedbar-expand-entity vhdl-speedbar-find-file 2 vhdl-speedbar-entity-face 0 " (top)" 1 "Packages:" vhdl-speedbar-make-pack-line 3 4] 11 (#$ . 294411)]) #@114 Insert hierarchy of project. Rescan directories if RESCAN is non-nil, otherwise use cached data of directories. (defalias 'vhdl-speedbar-insert-project-hierarchy #[(project &optional rescan) "\204�\305 \n\"\204�\305 \"\204�\306 \"\210\307\310\n \"\310 \"\310\f \"\311$\210\312 !\207" [rescan project vhdl-project-entity-alist vhdl-project-package-alist vhdl-project-ent-inst-list assoc vhdl-scan-project-contents vhdl-speedbar-insert-hierarchy aget 0 vhdl-speedbar-expand-units] 6 (#$ . 295142)]) #@99 Insert hierarchy of DIRECTORY. Rescan directory if RESCAN is non-nil, otherwise use cached data. (defalias 'vhdl-speedbar-insert-dir-hierarchy #[(directory depth &optional rescan) "\204�\306 \n\"\204�\306 \"\204�\307 !\210\310\311\n \"\311 \"\311\f \"@ $\210\312 !\207" [rescan directory vhdl-entity-alist vhdl-package-alist vhdl-ent-inst-alist depth assoc vhdl-scan-file-contents vhdl-speedbar-insert-hierarchy aget vhdl-speedbar-expand-units] 6 (#$ . 295653)]) #@77 Rescan hierarchy for the directory under the cursor or the current project. (defalias 'vhdl-speedbar-rescan-hierarchy #[nil "\303 \"A@\203�\304 \305\"\210\306 \207\212\307 \210\310\311!)\203,�\312\313\314\305#\210\315\316\317 !!\210\306 \207\317 \320\321\n\"\210\315\316\322\323\n\"!!\210\306 )\207" [vhdl-project-alist vhdl-project path aget vhdl-scan-project-contents t speedbar-refresh beginning-of-line looking-at "[^0-9]" re-search-forward "[0-9]+:" nil vhdl-scan-file-contents abbreviate-file-name speedbar-line-path string-match "^\\(.+/\\)" match-string 1] 5 (#$ . 296129) nil]) #@80 Expand subdirectories in DIRECTORY according to `speedbar-shown-directories'. (defalias 'vhdl-speedbar-expand-dirs #[(directory) "\305!A\306\n!C \2057�\307 @!\203/�\310 \210\311\312!\203/�\313\225b\210`\314\315\316 !!\317 \210* A\211\204�\320)\207" [speedbar-shown-directories sf default-directory position directory reverse expand-file-name speedbar-goto-this-file beginning-of-line looking-at "[0-9]+:\\s-*<" 0 abbreviate-file-name file-name-as-directory speedbar-line-file speedbar-do-function-pointer nil] 4 (#$ . 296725)]) #@82 Expand design units in DIRECTORY according to `vhdl-speedbar-shown-units-alist'. (defalias 'vhdl-speedbar-expand-units #[(directory) "\305 \"\306\300 \"\210\n\205_�\307 \n@@\"\210\310 \210\n@A@\311\312\313!\203X�\314\225b\210`\315 \210\f\203X� b\210\316\317\f@\320Q\311\321#\203Q�\310 \210\312\322!\203Q�\314\225b\210\315 \210\fA\211\2042�\nA*\202\n�)\207" [vhdl-speedbar-shown-units-alist directory ent-alist position arch-alist aget adelete vhdl-speedbar-goto-this-unit beginning-of-line nil looking-at "[0-9]+:\\s-*\\[" 0 speedbar-do-function-pointer re-search-forward "[0-9]+:\\s-*\\(\\[\\|{.}\\s-+" "\\>\\)" t "[0-9]+:\\s-*{"] 5 (#$ . 297267)]) #@46 Expand/contract the entity under the cursor. (defalias 'vhdl-speedbar-expand-entity #[(text token indent) "\306\307\"\203X\310 \n\"A@\203�\310 \n\"\202!�\310\f\311\312\313 !!!\"\314\310/\"80\315\310/\"81\316/ \"2\3173\3174\31750\204]�1\204]�2\204]�\320\321!\210\202S\320\322!\210\310 \n\"A@\203n�\n\202t�\311\312\313 !!6\3106\"\323\324\325 \317#\210\323\3266#\210*\3277\212\317\210\330u\2100\203\243�\331\332 T\"\2100\203\323�0@3\333\334\335\336/3@B3@\3373A@\31438B\340 T& \2100A\2110\204\250�1\203\336�\331\341 T\"\2101\2031@4\333\317\211\211/4@B4@\3374A@\31448B\342 T& \2101A\2111\204\343�2\203\331\343 T\"\2102\203J2@5\3445@5A@\31458\31558\34558\34658 T\347&\2102A\2112\204*\3178\212\350 \210).\202\250\306\351\"\203\244\320\335!\210\310 \n\"A@\203p\n\202v\311\312\313 !!6\3106\"\352\324\325 \"\210\203\226\323\3266#\210\202\234\352\3266\"\210*\353 !\210\202\250\354\355!\210\356 \207" [text vhdl-project-alist vhdl-project vhdl-project-entity-alist vhdl-entity-alist indent string-match "+" aget abbreviate-file-name file-name-as-directory speedbar-line-path 2 3 vhdl-get-instantiations nil speedbar-change-expand-button-char 63 45 aput ent-alist speedbar-line-text vhdl-speedbar-shown-units-alist t 1 vhdl-speedbar-make-title-line "Architectures:" speedbar-make-tag-line curly 43 vhdl-speedbar-expand-architecture vhdl-speedbar-find-file vhdl-speedbar-architecture-face "Configurations:" vhdl-speedbar-configuration-face "Instantiations:" vhdl-speedbar-make-inst-line 4 5 0 speedbar-stealthy-updates "-" adelete speedbar-delete-subblock error "No architectures, configurations, nor instantiations exist for this entity" speedbar-center-buffer-smartly token arch-alist conf-alist inst-alist arch-entry conf-entry inst-entry directory inhibit-read-only speedbar-last-selected-file] 11 (#$ . 297930)]) #@52 Expand/contract the architecture under the cursor. (defalias 'vhdl-speedbar-expand-architecture #[(text token indent) "\306\307\"\203\276�\310 @ A\311\n$\211\204�\312\313!\210\202\272�\312\314!\210\315 \306\316\f\"\317\320\f\")\321*+\"A@\203=�+\202C�\322\317\323\f\"!,\321,\"\321)\324#@-\325\326)\327 -BC#\210\325\330,#\210.\324.\212\331\210\323u\210 \203\201�\332\333\nT\"\210 \203\261� @/\334/@/A@\320/8\335/8\336/8\337/8\nT\340/8&\210 A)\202\201�*\3310\212\341 \210))\202#\306\342\"\203\312\343!\210\315 \306\316\f\"\317\320\f\")\321*+\"A@\203\347�+\202\355�\322\317\323\f\"!,\321,\"\321)\324#@-\325\326)\344\327 -\"C#\210\325\330,#\210.\345\n!\210\202#\346\347!\210\350 \207" [text token indent hier-alist path dummy string-match "+" vhdl-get-hierarchy 0 speedbar-change-expand-button-char 63 45 speedbar-line-path "^\\(.+/\\)\\([^/ ]+\\)" match-string 2 aget abbreviate-file-name 1 t aput ent-alist speedbar-line-text vhdl-speedbar-shown-units-alist nil vhdl-speedbar-make-title-line "Subcomponents:" vhdl-speedbar-make-inst-line 3 4 5 6 speedbar-stealthy-updates "-" 43 delete speedbar-delete-subblock error "No component instantiations contained in this architecture" speedbar-center-buffer-smartly ent-name vhdl-project-alist vhdl-project directory arch-alist inhibit-read-only entry speedbar-last-selected-file] 11 (#$ . 299837)]) #@121 Highlight all design units that are contained in the current file. NO-POSITION non-nil means do not re-position cursor. (defalias 'vhdl-speedbar-update-current-unit #[(&optional no-position) "\306 \307\211\310 !\210\311\312 \206�\313!\211\f\232\204\317�\310 !\210\"q\210\314#\212\315$\f\"%\316\317%@\f\320$\210\316\321%A@\f\322$\210\316\323\324%8\f\325$\210\316\323\326%8\f\327$\210\316\323\330%8\f\331$\210)\315$ \"%\316\317%@ \332$\210\206u�\333 \316\321%A@ \334$\210\206\206�\333 \316\323\324%8 \335$\210\206\227�\333 \316\323\326%8 \336$\210\206\250�\333 \316\323\330%8 \337$\210+\206\272�\333 \211\203\315�&\204\315�b\210\340 \210\341 \210 \310\n!\210+\314\207" [position file-name last-frame speedbar-attached-frame speedbar-last-selected-file speedbar-frame selected-frame nil select-frame abbreviate-file-name buffer-file-name "" t aget vhdl-speedbar-update-units "\\[.\\]" vhdl-speedbar-entity-face "{.}" vhdl-speedbar-architecture-face ">" 2 vhdl-speedbar-configuration-face 3 vhdl-speedbar-package-face 4 vhdl-speedbar-instantiation-face vhdl-speedbar-entity-selected-face point-marker vhdl-speedbar-architecture-selected-face vhdl-speedbar-configuration-selected-face vhdl-speedbar-package-selected-face vhdl-speedbar-instantiation-selected-face speedbar-center-buffer-smartly speedbar-position-cursor-on-line speedbar-buffer inhibit-read-only vhdl-file-alist file-entry no-position] 6 (#$ . 301249)]) #@42 Help function to highlight design units. (defalias 'vhdl-speedbar-update-units #[(text unit-list file-name face) "\305 \203;�eb\210\306\n\307 @\310R\305\311#\2034� \312\313\224\314\"@\232\203 �\206'�\315 \316\313\224\313\225\304\f$\210\202 � A\211\204�\205A�b)\207" [position unit-list text file-name face nil re-search-forward " \\(" "\\)\\>" t get-text-property 1 speedbar-token point-marker put-text-property] 6 (#$ . 302703)]) #@29 Insert instantiation entry. (defalias 'vhdl-speedbar-make-inst-line #[(inst-name inst-file-marker ent-name ent-file-marker arch-name arch-file-marker depth offset) "`\306 !\307\261\210\310`\311\312$\210`\313\314 \n _\\\"\210\315c\210\310`\311\316$\210`\fc\210\317`\320\321\322 &\210`\323c\210\310`\311\316$\210`c\210\317`\324\321\322&\210`\203x�\325c\210\310`\311\316$\210`c\210\317`\326\321\322&\210`\327c\210\310`\311\316$\210\313\330\331\"\210\310`S`\311\316$)\207" [start depth offset vhdl-speedbar-hierarchy-indent inst-name inst-file-marker int-to-string ":" put-text-property invisible t insert-char 32 "> " nil speedbar-make-button vhdl-speedbar-instantiation-face speedbar-highlight-face vhdl-speedbar-find-file ": " vhdl-speedbar-entity-face " (" vhdl-speedbar-architecture-face ")" 10 1 ent-name ent-file-marker arch-name arch-file-marker] 7 (#$ . 303147)]) #@23 Insert package entry. (defalias 'vhdl-speedbar-make-pack-line #[(pack-name pack-file-marker body-file-marker depth) "`\305 !\306\261\210\307`\310\311$\210`\312\313 \"\210\314c\210\307`\310\315$\210`\nc\210\316`\317\320\321 &\210\f@\203\\�`\322c\210\307`\310\315$\210`\323c\210\316`\317\320\321\f&\210`\324c\210\307`\310\315$\210\312\325\326\"\210\307`S`\310\315$)\207" [start depth pack-name pack-file-marker body-file-marker int-to-string ":" put-text-property invisible t insert-char 32 "> " nil speedbar-make-button vhdl-speedbar-package-face speedbar-highlight-face vhdl-speedbar-find-file " (" "body" ")" 10 1] 7 (#$ . 304052)]) #@33 Insert design unit title entry. (defalias 'vhdl-speedbar-make-title-line #[(text depth) "`\303 !\304\261\210\305`\306\307$\210`\310\311 \"\210\305`\306\312$\210`\nc\210\313`\312\211\211\211&\210\310\314\315\"\210\305`\306\312$)\207" [start depth text int-to-string ":" put-text-property invisible t insert-char 32 nil speedbar-make-button 10 1] 7 (#$ . 304707)]) #@24 Insert subdirectories. (defalias 'vhdl-speedbar-insert-dirs #[(files level) "@\211\205�\303\304\305\306 @ @\307\310\311\n& \210 A\211\204�\310)\207" [files dirs level speedbar-make-tag-line angle 43 vhdl-speedbar-dired speedbar-dir-follow nil speedbar-directory-face] 11 (#$ . 305085)]) #@71 Speedbar click handler for directory expand button in hierarchy mode. (defalias 'vhdl-speedbar-dired #[(text token indent) "\306\307\"\203L�\310\311 !\n\312Q! B\313\314!\210\315 \210\316\212\317\210\320u\210\321\322\311 !\n\312Q! T\"\210\315 \210\323\324\311 !\n\312Q! T #\210*\317\212\325 \210)\202\234�\306\326\"\203\230�\315 \210 \317\310\311 !\nP! \211!\203\210�\306\327\330!P!@\"\204�!@ B !A\211!\204i� \237+\313\331!\210\332 !\210\202\234�\333\334!\210\335 \207" [text indent token speedbar-shown-directories inhibit-read-only speedbar-power-click string-match "+" expand-file-name speedbar-line-path "/" speedbar-change-expand-button-char 45 speedbar-reset-scanners t nil 1 vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy abbreviate-file-name speedbar-stealthy-updates "-" "^" regexp-quote 43 speedbar-delete-subblock error "Ooops... not sure what to do" speedbar-center-buffer-smartly speedbar-last-selected-file td newl oldl] 6 (#$ . 305383)]) #@54 Derive and display information about this line item. (defalias 'vhdl-speedbar-item-info #[nil "\212\303 \210\304\305!\203�\306\225b\210\304\307!\203�\310\311\312 \"@\"\210\304\313!\203(�\314 \202\240�\304\315!\205\240�\306\225b\210\316`\302\"\310\317\n\320=\204E�\n\321=\203I�\322\202\212�\n\323=\204U�\n\324=\203Y�\325\202\212�\n\326=\204e�\n\327=\203i�\330\202\212�\n\331=\204u�\n\332=\203y�\333\202\212�\n\334=\204\205�\n\335=\203\211�\336\202\212�\337\340`\304\341!\210\306\225\"\342\316`\343\"@\206\235�\344!$))\207" [vhdl-project-alist vhdl-project face beginning-of-line looking-at "[0-9]+:" 0 "p:" message "Project \"%s\"" aget "\\s-*<[-+?]> " speedbar-files-item-info "\\s-*\\([[{][-+?][]}]\\|>\\) " get-text-property "%s \"%s\" in \"%s\"" vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face "Entity" vhdl-speedbar-architecture-face vhdl-speedbar-architecture-selected-face "Architecture" vhdl-speedbar-configuration-face vhdl-speedbar-configuration-selected-face "Configuration" vhdl-speedbar-package-face vhdl-speedbar-package-selected-face "Package" vhdl-speedbar-instantiation-face vhdl-speedbar-instantiation-selected-face "Instantiation" "" buffer-substring-no-properties "\\(\\w\\|_\\)+" abbreviate-file-name speedbar-token "?"] 8 (#$ . 306398)]) #@46 Recursively get subdirectories of DIRECTORY. (defalias 'vhdl-get-subdirs #[(directory) "\304!C\305\211\306\307\310#\211\203)�\311 @!\203\"�\312 \313 @!\" A\211\204� +\207" [directory file-list subdir-list dir-list file-name-as-directory nil vhdl-directory-files t "\\w.*" file-directory-p append vhdl-get-subdirs] 5 (#$ . 307680)]) #@64 Resolve environment variables and path wildcards in PATH-LIST. (defalias 'vhdl-resolve-paths #[(path-list) "\306\211\211\211\211\211\203<�@\307\310\"\203/�\311\312\"\313\311\314\"!\311\315\"Q\202� BA\211\204� \203g� @\307\316\"\210\317\311\314\"!\203X�\fB\202`�\320\321\311\314\"\"\210 A\211\204@�\f\203\330�\f@\307\322\"\203\277�\311\312\"\311\323\"\324\325\326\327\311\314\"\330\331\332\311\315\"!P#\306\211\203\263�\317@!\203\252�@BA\211\204\232�*\"\fA\"\211\202h�\307\333\"\210\317\311\314\"!\203\321� B\fA\211\204k� .\207" [dir path-end path-beg path-list-3 path-list-2 path-list-1 nil string-match "\\(.*\\)${?\\(\\(\\w\\|_\\)+\\)}?\\(.*\\)" match-string 1 getenv 2 4 "\\(-r \\)?\\(\\([^?*]*/\\)*\\)" file-directory-p message "No such directory: \"%s\"" "\\(-r \\)?\\(\\([^?*]*/\\)*\\)\\([^/]*[?*][^/]*\\)\\(/.*\\)" 5 append mapcar #[(var) " \nQ\207" [path-beg var path-end] 3] vhdl-directory-files t "\\<" wildcard-to-regexp "\\(-r \\)?\\(.*\\)/.*" path-list dir-list all-list] 12 (#$ . 308027)]) #@111 Append a key-value pair to an alist. Similar to `aput' but moves the key-value pair to the tail of the alist. (defalias 'vhdl-aappend #[(alist-symbol key value) "\305 \"\306\n\"\n\307 \f\"L*\207" [key value alist-symbol alist elem aelement adelete append] 4 (#$ . 309103)]) #@75 If UNIT is displayed in DIRECTORY, goto this line and return t, else nil. (defalias 'vhdl-speedbar-goto-this-unit #[(directory unit) "`\305 \n\"A@\203�eb\210\202�\306 !\203)�\307\310\f\311Q\312\313#\203)�\314 \210\313\202-�b\210\312)\207" [dest vhdl-project-alist vhdl-project directory unit aget speedbar-goto-this-file re-search-forward "[]}] " "\\>" nil t speedbar-position-cursor-on-line] 4 (#$ . 309387)]) #@70 When user clicks on TEXT, load file with name and position in TOKEN. (defalias 'vhdl-speedbar-find-file #[(text token indent) "@\204 �\302\303!\207\304@!\210\305A!\210\306 \210\307\310!\210\311 !\210\312 \207" [token speedbar-update-speed error "Design unit does not exist" speedbar-find-file-in-frame goto-line recenter vhdl-speedbar-update-current-unit t speedbar-set-timer speedbar-maybee-jump-to-attached-frame] 2 (#$ . 309808)]) #@50 Toggle between hierarchy and file browsing mode. (defalias 'vhdl-speedbar-toggle-hierarchy #[nil "\301\302!\204\n�\303\304!\207\305\232\203�\306\307!\207\306\305!\207" [speedbar-initial-expansion-list-name boundp speedbar-mode-functions-list error "WARNING: Install included `speedbar.el' patch first" "vhdl hierarchy" speedbar-change-initial-expansion-list "files"] 2 (#$ . 310251) nil]) #@47 Copy the port of the entity under the cursor. (defalias 'vhdl-speedbar-port-copy #[nil "\300 \210\301\302\212\303\210`)\304#\203�\303\305\306\217\207\307\310!\207" [beginning-of-line re-search-forward "\\([0-9]\\)+:\\s-*\\[[-+?]\\] \\(\\(\\w\\|\\s_\\)+\\)" nil t (byte-code "\306\307\310!!\307\311!\312\n \"A@\203�\312\f \"\202$�\312 \313\314\315!!!\"\312 \"\211@\316 \317!\203D�\320!q\210\202d�\321\316\322#q\210\323\324\325\326 #\210\323\327\330\326 #\210\323\331\330\326 #\210\322 \332A@!\210\316\210\333 \210 \205y�\334p!.\207" [indent ent-name vhdl-project-alist vhdl-project vhdl-project-entity-alist vhdl-entity-alist string-to-number match-string 1 2 aget abbreviate-file-name file-name-as-directory speedbar-line-path nil find-buffer-visiting file-name-nondirectory find-file-noselect t modify-syntax-entry 45 ". 12" syntax-table 10 ">" 13 goto-line vhdl-port-copy kill-buffer ent-alist ent-entry file-name opened] 7) ((error (error "Port not scanned successfully"))) error "No entity on current line"] 4 (#$ . 310649) nil]) (byte-code "\300\301\302\303\304\305%\210\300\306\307\310\304\305%\210\300\311\312\313\304\305%\210\300\314\315\316\304\305%\210\300\317\320\321\304\305%\210\300\322\323\303\304\305%\210\300\324\325\310\304\305%\210\300\326\327\313\304\305%\210\300\330\331\316\304\305%\210\300\332\333\321\304\305%\207" [custom-declare-face vhdl-speedbar-entity-face ((((class color) (background light)) (:foreground "ForestGreen")) (((class color) (background dark)) (:foreground "PaleGreen"))) "Face used for displaying entity names." :group speedbar-faces vhdl-speedbar-architecture-face ((((class color) (background light)) (:foreground "Blue")) (((class color) (background dark)) (:foreground "LightSkyBlue"))) "Face used for displaying architecture names." vhdl-speedbar-configuration-face ((((class color) (background light)) (:foreground "DarkGoldenrod")) (((class color) (background dark)) (:foreground "Salmon"))) "Face used for displaying configuration names." vhdl-speedbar-package-face ((((class color) (background light)) (:foreground "Grey50")) (((class color) (background dark)) (:foreground "Grey80"))) "Face used for displaying package names." vhdl-speedbar-instantiation-face ((((class color) (background light)) (:foreground "Brown")) (((class color) (background dark)) (:foreground "Yellow"))) "Face used for displaying instantiation names." vhdl-speedbar-entity-selected-face ((((class color) (background light)) (:foreground "ForestGreen" :underline t)) (((class color) (background dark)) (:foreground "PaleGreen" :underline t))) vhdl-speedbar-architecture-selected-face ((((class color) (background light)) (:foreground "Blue" :underline t)) (((class color) (background dark)) (:foreground "LightSkyBlue" :underline t))) vhdl-speedbar-configuration-selected-face ((((class color) (background light)) (:foreground "DarkGoldenrod" :underline t)) (((class color) (background dark)) (:foreground "Salmon" :underline t))) vhdl-speedbar-package-selected-face ((((class color) (background light)) (:foreground "Grey50" :underline t)) (((class color) (background dark)) (:foreground "Grey80" :underline t))) vhdl-speedbar-instantiation-selected-face ((((class color) (background light)) (:foreground "Brown" :underline t)) (((class color) (background dark)) (:foreground "Yellow" :underline t)))] 6) #@36 Address for VHDL Mode bug reports. (defconst vhdl-mode-help-address "vhdl-mode@geocities.com" (#$ . 314016)) #@58 Echo the current version of VHDL Mode in the minibuffer. (defalias 'vhdl-version #[nil "\301\302\"\210\303 \207" [vhdl-version message "Using VHDL Mode version %s" vhdl-keep-region-active] 3 (#$ . 314131) nil]) #@44 Submit via mail a bug report on VHDL Mode. (defalias 'vhdl-submit-bug-report #[nil "\302\303!\205\252�\304\305!\205\252�\306\307 P\310\311\312\313\314\315\316\317\320\321\322\323\324\325\326\327\330\331\332\333\334\335\336\337\340\341\342\343\344\345\346\347\350\351\352\353\354\355\356\357\360\361\362\363\364\365\366\367\370\371\372\373\374\375\376\377\201@�\201A�\201B�\201C�\201D�\201E�\201F�\201G�\201H�\201I�\201J�\201K�\201L�\201M�\201N�\201O�\201P�\201Q�\201R�\201S�\201T�\201U�\201V�\201W�\201X�\201Y�\201Z�\201[�\257T\201\\�\201]�\201^�&\207" [vhdl-mode-help-address vhdl-version y-or-n-p "Do you want to submit a report on VHDL Mode? " require reporter reporter-submit-bug-report "VHDL Mode " vhdl-offsets-alist vhdl-comment-only-line-offset tab-width vhdl-electric-mode vhdl-stutter-mode vhdl-indent-tabs-mode vhdl-project-alist vhdl-project vhdl-compiler-alist vhdl-compiler vhdl-compiler-options vhdl-standard vhdl-basic-offset vhdl-upper-case-keywords vhdl-upper-case-types vhdl-upper-case-attributes vhdl-upper-case-enum-values vhdl-upper-case-constants vhdl-electric-keywords vhdl-optional-labels vhdl-insert-empty-lines vhdl-argument-list-indent vhdl-association-list-with-formals vhdl-conditions-in-parenthesis vhdl-zero-string vhdl-one-string vhdl-file-header vhdl-file-footer vhdl-company-name vhdl-platform-spec vhdl-date-format vhdl-modify-date-prefix-string vhdl-modify-date-on-saving vhdl-reset-kind vhdl-reset-active-high vhdl-clock-rising-edge vhdl-clock-edge-condition vhdl-clock-name vhdl-reset-name vhdl-model-alist vhdl-include-port-comments vhdl-include-direction-comments vhdl-actual-port-name vhdl-instance-name vhdl-testbench-entity-name vhdl-testbench-architecture-name vhdl-testbench-dut-name vhdl-testbench-entity-header vhdl-testbench-architecture-header vhdl-testbench-declarations vhdl-testbench-statements vhdl-testbench-initialize-signals vhdl-testbench-create-files vhdl-self-insert-comments vhdl-prompt-for-comments vhdl-inline-comment-column vhdl-end-comment-column vhdl-auto-align vhdl-align-groups vhdl-highlight-keywords vhdl-highlight-names vhdl-highlight-special-words vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-translate-off vhdl-highlight-case-sensitive vhdl-special-syntax-alist vhdl-forbidden-words vhdl-forbidden-syntax vhdl-speedbar vhdl-speedbar-show-hierarchy vhdl-speedbar-hierarchy-indent vhdl-index-menu vhdl-source-file-menu vhdl-hideshow-menu vhdl-hide-all-init vhdl-print-two-column vhdl-print-customize-faces vhdl-intelligent-tab vhdl-word-completion-case-sensitive vhdl-word-completion-in-minibuffer vhdl-underscore-is-part-of-word vhdl-mode-hook vhdl-startup-warnings #[nil "\203�\301\302\303\304\"\305\306\260\202�\307c\207" [vhdl-special-indent-hook "\n@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" "vhdl-special-indent-hook is set to '" format "%s" ".\nPerhaps this is your problem?\n" "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n\n" "\n"] 5] nil "Dear VHDL Mode maintainers,"] 87 (#$ . 314349) nil]) (provide 'vhdl-mode)